代码搜索：CAN Bus
找到约 10,000 项符合「CAN Bus」的源代码
代码结果 10,000
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v can_defines.v
// Uncomment following line if you want to use WISHBONE interface. Otherwise
// 8051 interface is used.
// `define CAN_WISHBONE_IF
// Uncomment following line if you want to use CAN in Ac
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prj can_top.prj
verilog work can_register_asyn_syn.v
verilog work can_register_asyn.v
verilog work can_register.v
verilog work can_registers.v
verilog work can_btl.v
verilog work can_crc.v
verilog work can_acf.
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ngd can_top.ngd
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v can_registers.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
module can_registers
(
clk,
rst,
cs,
we,
addr,
data_in,
data_out,
i
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prj can_registers.prj
verilog work can_register_asyn_syn.v
verilog work can_register_asyn.v
verilog work can_register.v
verilog work can_registers.v
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ndo can_testbench.ndo
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model for Module can_top
vcom -87 -explicit can_t
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v can_ibo.v
// This module only inverts bit order
module can_ibo
(
di,
do
);
input [7:0] di;
output [7:0] do;
assign do[0] = di[7];
assign do[1] = di[6];
assign do[2] = di[5];
assign do