代码搜索：CAN Bus
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udo can_testbench.udo
## Project Navigator simulation template: can_testbench.udo
## You may edit this file to control your simulation.
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ngr can_fifo.ngr
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v can_fifo.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
module can_fifo
(
clk,
rst,
wr,
data_in,
addr,
data_out,
fifo_sele
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ngr can_top.ngr
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v can_top.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
module can_top
(
`ifdef CAN_WISHBONE_IF
wb_clk_i,
wb_rst_i,
wb_dat_i,
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v can_btl.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
module can_btl
(
clk,
rst,
rx,
/* Mode register */
reset_mode,
/* Bus
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ldo can_top.ldo
# Auto generated by Project Navigator for Modelsim
vlib work
vlog can_register_asyn_syn.v
vlog can_register_asyn.v
vlog can_register.v
vlog can_registers.v
vlog can_btl.v
vlog can_crc.v
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ngc can_top.ngc
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syr can_top.syr
Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.20 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to
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v can_bsp.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
module can_bsp
(
clk,
rst,
sample_point,
sampled_bit,
sampled_bit_q,
tx