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Buck 的代码
test buck closed-loop cm.net
* source CHAPTER 2_1
L_L1 VOUT N8198841 35u
X_U12 N816754 N817146 0 ERR DUTY PWMCMX PARAMS: L=35u FS=100k RI=1
+ SE=0
R_R5 N817146 N8198841 20m
R_Rlower 0
test buck closed-loop cm.als
.ALIASES
L_L1 L1(1=VOUT 2=N8198841 ) CN @CHAPTER 2_1.test buck closed-loop CM(sch_1):INS819874@ANALOG.L.Normal(chips)
X_U12 U12(A=N816754 C=N817146 P=0 VC=ERR DC=DUTY ) CN @CHAP
test buck closed-loop cm.sim
@OrCAD Simulation Server Version: 1.0
@Settings: 0 1
@General:
ProfileName= "test buck closed-loop CM"
ProfileFile= "test buck closed-loop cm.sim"
Connectivity= "test buck closed-loop CM.net"
basic ccm-dcm buck_sch.prp
("FILE_TYPE" "PMAP File"
("devices"
("VDC")
("PWMVM")
("R"
("info"
("spice_dsg" "R")
("port_order"
(
test buck closed-loop vm.prb
[DISPLAYS]
BEGIN DISPLAY LAST SESSION
ANALYSIS TRANSIENT_ANALYSIS
SYMBOL ALWAYS
TRACECOLORSCHEME NORMAL
BEGIN ANAPLOT 1
ACTIVE
XBASE
BEGIN XAXIS
XAXISUSERNAME 0 (null)
RANGEFLAG AUTO
TYPE L
test buck closed-loop vm.sim
@OrCAD Simulation Server Version: 1.0
@Settings: 0 1
@General:
ProfileName= "test buck closed-loop VM"
ProfileFile= "test buck closed-loop VM.sim"
Connectivity= "test buck closed-loop tran VM
test buck cycle-by-cycle vm.als
.ALIASES
L_L1 L1(1=VOUT 2=N716813 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS731909@ANALOG.L.Normal(chips)
V_V7 V7(+=N716967 -=0 ) CN @CHAPTER 2_1.test buck cycle-
test buck cycle-cycle vm.mif
lib="D:\Christophe\Livres\Spice simus 2\Chapter2\Simulation examples\PSpice\application.lib", offset=1797, size=23
lib="D:\Christophe\Livres\Spice simus 2\Chapter2\Simulation examples\PSpice\applic