代码搜索：Behavior
找到约 3,820 项符合「Behavior」的源代码
代码结果 3,820
www.eeworm.com/read/484688/6572583
vhd fenwei2.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Fenwei2 IS
PORT(Numin:IN integer RANGE 0 TO 63;
NumC,NumD:OUT Integer RANGE 0 to 9);
END ENTITY;
ARCHITECTURE behavior OF Fenwei2 IS
www.eeworm.com/read/483255/6602586
vhd fenwei2.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Fenwei2 IS
PORT(Numin:IN integer RANGE 0 TO 64;
NumA,NumB:OUT Integer RANGE 0 to 9);
END ENTITY;
ARCHITECTURE behavior OF Fenwei2 IS
B
www.eeworm.com/read/478253/6722781
vhd x_or2.vhd
library ieee;
use ieee.std_logic_1164.all;
entity x_or2 is
port (
in1 : in bit ;
in2 : in bit ;
out1 : out bit) ;
end x_or2;
entity and_gate is
port (
a : in bit ;
b : in bit ;
c :
www.eeworm.com/read/261198/11659492
m mysize.m
function sz = mysize(M)
% MYSIZE Like the built-in size, except it returns n if M is a vector of length n, and 1 if M is a scalar.
% sz = mysize(M)
%
% The behavior is best explained by examples
% -
www.eeworm.com/read/343492/11944289
m mysize.m
function sz = mysize(M)
% MYSIZE Like the built-in size, except it returns n if M is a vector of length n, and 1 if M is a scalar.
% sz = mysize(M)
%
% The behavior is best explained by examples
% -
www.eeworm.com/read/252132/12300230
vhd flipflop.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Resetn, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END flipflop ;
ARCHITECTURE Behavior OF flipfl
www.eeworm.com/read/252132/12300355
vhd priority.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY priority IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z : OUT STD_LOGIC ) ;
END priorit
www.eeworm.com/read/252132/12300448
vhd flipflop.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Resetn, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC ) ;
END flipflop ;
ARCHITECTURE Behavior OF flipf
www.eeworm.com/read/252132/12300547
vhd adder16.vhd
ENTITY adder16 IS
PORT ( X, Y : IN INTEGER RANGE -32768 TO 32767 ;
S : OUT INTEGER RANGE -32768 TO 32767 ) ;
END adder16 ;
ARCHITECTURE Behavior OF adder16 IS
BEGIN
S
www.eeworm.com/read/252132/12300578
vhd downcnt.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL ;
ENTITY downcnt IS
GENERIC ( initial_count : INTEGER := 16 ) ;
PORT ( Clock, E, L : IN STD_LOGIC ;
Q : BUFFER INTEGER RANGE 0 TO initial_co