代码搜索：Async
找到约 3,194 项符合「Async」的源代码
代码结果 3,194
www.eeworm.com/read/369664/9637394
v async_cmp.v
// 异步比较器
module async_cmp (aempty_n, afull_n, wptr, rptr, wrst_n);
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
output aempty_n, afull_n;
input [N:0] wptr, rptr;
input wrst_n;
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c test_async.c
/*
** 2005 December 14
**
** The author disclaims copyright to this source code. In place of
** a legal notice, here is a blessing:
**
** May you do good and not evil.
** May you find forgivene
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test async2.test
#
# May you do good and not evil.
# May you find forgiveness for yourself and forgive others.
# May you share freely, never taking more than you give.
#
#*************************************
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v async_receiver.v
// RS-232 RX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
input clk, RxD;
output RxD_data_re
www.eeworm.com/read/335066/12551226
v async_transmitter.v
module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy);
input clk, TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;
parameter ClkFrequency = 50000000; // 50MHz
//parameter ClkF
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v async_receiver.v
module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
input clk, RxD;
output RxD_data_ready; // onc clock pulse when RxD_data is valid
output [7:0] RxD_data;
par
www.eeworm.com/read/248574/12552620
v async_transmitter.v
module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy);
input clk, TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud =
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gif async-start.gif
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gif async-sr.gif
www.eeworm.com/read/248574/12552627