代码搜索：Async
找到约 3,194 项符合「Async」的源代码
代码结果 3,194
www.eeworm.com/read/350798/3115847
pjt async_pci.pjt
; Code Composer Project File, Version 2.0 (do not modify or remove this line)
[Project Settings]
ProjectName="async_pci"
ProjectDir="c:\ti\ddk\apps\port\vt1423_pci\"
ProjectType=Executable
CPUF
www.eeworm.com/read/350798/3115854
c async_pci.c
/*
* Copyright 2003 by Texas Instruments Incorporated.
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
*
www.eeworm.com/read/266151/4274278
sgml async_queues.sgml
Asynchronous Queues
asynchronous communication between threads.
www.eeworm.com/read/261925/4319331
py async_processor.py
# An async command processor
from dlgutils import *
import win32gui, win32api, win32con, commctrl
import win32process
import time
import processors
try:
True, False
except NameError:
# Maint
www.eeworm.com/read/155397/5622409
c async_rcvr.c
/*
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING.
* By downloading, copying, installing or using the software you agree to this
* license. If you do not agree to this license, d
www.eeworm.com/read/395931/8145673
v async_fifo.v
// FIFO顶层模块
module async_fifo (rdata, wfull, rempty, wdata,
wreq, wclk, wrst_n, rreq, rclk, rrst_n);
parameter DATA_WIDTH = 8; // FIFO数据位宽
parameter ADDR_WIDTH = 4; // FIFO地址位宽
output
www.eeworm.com/read/395931/8145676
v async_cmp.v
// 异步比较器
module async_cmp (aempty_n, afull_n, wptr, rptr, wrst_n);
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
output aempty_n, afull_n;
input [N:0] wptr, rptr;
input wrst_n;
www.eeworm.com/read/395559/8168216
v async_fifo.v
// FIFO顶层模块
module async_fifo (rdata, wfull, rempty, wdata,
wreq, wclk, wrst_n, rreq, rclk, rrst_n);
parameter DATA_WIDTH = 8; // FIFO数据位宽
parameter ADDR_WIDTH = 4; // FIFO地址位宽
output
www.eeworm.com/read/395559/8168218
v async_cmp.v
// 异步比较器
module async_cmp (aempty_n, afull_n, wptr, rptr, wrst_n);
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
output aempty_n, afull_n;
input [N:0] wptr, rptr;
input wrst_n;
www.eeworm.com/read/369664/9637393
v async_fifo.v
// FIFO顶层模块
module async_fifo (rdata, wfull, rempty, wdata,
wreq, wclk, wrst_n, rreq, rclk, rrst_n);
parameter DATA_WIDTH = 8; // FIFO数据位宽
parameter ADDR_WIDTH = 4; // FIFO地址位宽
output