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analog_comparators_out_reg.lnp

".\obj\startup.o" ".\obj\analog_comparators_out_reg.o" --device DLM --strict --scatter ".\obj\Analog_Comparators_out_reg.sct" --autoat --summary_stderr --info summarysizes --map --xref --callgraph -

analog_comparators_out_reg.map

ARM Linker, RVCT3.1 [Build 903] for uVision [Standard] ================================================================================ Section Cross References startup.o(STACK) refers (S

analog_comparators_out_reg.hex

:0400000500000000F7 :020000040000FA :1000000060010020B9000000BD000000BF0000003A :10001000C1000000C1000000C1000000000000009D :10002000000000000000000000000000C10000000F :10003000C100000000000000C1

analog_comparators_out_reg.plg

礦ision3 Build Log Project: F:\kangqinhua\EasyARM8962_V1.00\DEMO\keil实验例程\chapter4\4.13.2_Analog_Comparators_out\Analog_Comparators_out_reg\Analog_Comparators

analog_comparators_out_reg.c

/****************************************Copyright (c)**************************************************** ** Guangzhou ZHIYUAN electronics Co.,LTD. **

analog_comparators_out_reg.opt

### uVision2 Project, (C) Keil Software ### Do not modify ! cExt (*.c) aExt (*.s*; *.src; *.a*) oExt (*.obj) lExt (*.lib) tExt (*.txt; *.h; *.inc) pExt (*.plm) CppX (*.cpp) DaveTm {

analog_models3_transient.deck

Code Model Test - Transient: hyst, limit, ilimit, climit, cmeter, lmeter * * *** analysis type *** .tran .1s 15s * *** input sources *** * v1 1 0 DC PWL(0 0 15 15) * v2 2 0 DC 10.0 * v3 3 0 DC -10.0

analog_models4_transient.deck

Code Model Test - Transient: sine, triangle, aswitch, zener, oneshot * * *** analysis type *** .tran .01ms 2ms * *** input sources *** * v1 1 0 DC 0.0 PWL(0 0 2e-3 2) * v2 2 0 DC 0.0 PWL(0 0 2e-3 10)

analog_models2_ac.deck

Code Model Test - Swept DC: int, d_dt, s_xfer, core, lcouple * * *** analysis type *** .ac dec 10 10 1000 * * *** input sources *** * v1 1 0 1.0 AC 1.0 0.0 * * *** integrator block *** a1 1 10 int1 .

analog_models1_ac.deck

Code Model Test - AC: gain, summer, mult, divide, pwl * * *** analysis type *** .ac dec 10 10 1000 * *** input sources *** * v1 1 0 1.0 AC 1.0 0.0 * v2 2 0 1.0 AC 1.0 0.0 * v3 3 0 DC 2.0 * v4 4 0 0.5