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// Sinc3 Filter // (c) Analog Devices AD7401 Datasheet // Modified by Charles HY Cheung, Cornell University /*`Data is read on negative clk edge*/ module DEC256SINC24B(mclk1, reset, rate, mdata1

% Analog Signal Dt = 0.00005; t = -0.005:Dt:0.005; xa = exp(-1000*abs(t)); % Discrete-time Signal Ts = 0.001; n = -5:1:5; x = exp(-1000*abs(n*Ts)); % Discrete-time Fourier transform K = 500; k

% Analog Signal Dt = 0.00005; t = -0.005:Dt:0.005; xa = exp(-1000*abs(t)); % Discrete-time Signal Ts = 0.001; n = -5:1:5; x = exp(-1000*abs(n*Ts)); % Discrete-time Fourier transform K = 500; k

Build target 'Target 1' compiling ANALOG.C... compiling ARP.C... compiling ETH.C... compiling HTTP.C... compiling ICMP.C... compiling IP.C... compiling MAIN.C... compiling SERIAL.C... compili

# Generated by the VisualDSP++ IDDE (Wed Nov 08 09:59:56 2006) # Project File: D:\Program Files\Analog Devices\VisualDSP 4.5\Blackfin\Examples\ADSP-BF561 EZ-KIT Lite\Services\DMA\memory_DMA_1D\CoreA\

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% Analog Signal Dt = 0.00005; t = -0.005:Dt:0.005; xa = exp(-1000*abs(t)); % Discrete-time Signal Ts = 0.0002; n = -25:1:25; x = exp(-1000*abs(n*Ts)); % Discrete-time Fourier transform K = 500; k = 0: