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f206fullc.dat
1TITLEWatchdog Timer Configuration
2Select Timeout Interval
3Timeout Interval: 1048576 x Tsysclk[FF=07,FF]D
3Timeout Interval: 262144 x Tsysclk[FF=06,FF]
3Timeout Interval: 65636 x Tsys
f226full.dat
1TITLEWatchdog Timer Configuration
2Select Timeout Interval
3Timeout Interval: 1048576 x Tsysclk[FF=07,FF]D
3Timeout Interval: 262144 x Tsysclk[FF=06,FF]
3Timeout Interval: 65636 x Tsys
gnd.1
V 50
K 296682930300 GND
Y 4
D 0 0 40 40
Z 10
i 4
U 0 -20 10 0 1 0 CLASS=ANALOG
U 0 -30 10 0 3 0 GND
U -10 -20 10 0 3 0 PINORDER=GND
l 2 35 10 5 10
l 2 40 20 0 20
l 2 25 2 15 2
U -10 -40 10
res-4.1
V 51
K 238202325300 res-4
|R 17:05_11-29-05
Y 1
D -30 0 70 50
Z 10
i 8
U 0 0 9 0 3 0 DEVICE=RPACK4
U 0 0 9 0 3 0 PARTS=1
U 0 0 0 0 3 0 SOURCE_PATH
U 0 0 9 0 3 0 PINSWAP=(1,8,2,7,3,6,4,5)
U
cap_np.1
V 51
K 339944573700 cap_np
|R 17:04_10-27-05
Y 1
D 0 0 40 30
Z 10
i 4
U 0 -10 10 0 3 0 DEVICE=CAP_NP
U 0 -20 10 0 1 0 PARTS=1
U 0 -30 10 0 1 0 LEVEL=STD
U 41 26 10 2 5 3 REFDES=C?
U 30 10 1
fg_06_03poles.m
% fg_06_03poles Expressions for analog Butterworth poles.
L=6;
a=[1, zeros(1,2*L-1), 1];
power_poles=roots(a)';
poles=power_poles(1:L)
sd16.c
/********************************************************************************
* 杭州利尔达 *
* MSP430FE42X单相防窃电多功能电表平台
coreb.c
/*******************************************************************************
Copyright(c) 2005 Analog Devices. All Rights Reserved.
Developed for Blackfin DSPs ( Micro Signal Architecture).
coreb.c
/*******************************************************************************
Copyright(c) 2005 Analog Devices. All Rights Reserved.
Developed for Blackfin DSPs ( Micro Signal Architecture).
coreb.c
/*******************************************************************************
Copyright(c) 2005 Analog Devices. All Rights Reserved.
Developed for Blackfin DSPs ( Micro Signal Architecture).