代码搜索：Addressing
找到约 974 项符合「Addressing」的源代码
代码结果 974
www.eeworm.com/read/350097/3131901
h acenic.h
#ifndef _ACENIC_H_
#define _ACENIC_H_
/*
* Addressing:
*
* The Tigon uses 64-bit host addresses, regardless of their actual
* length, and it expects a big-endian format. For 32 bit systems the
*
www.eeworm.com/read/347503/3171174
s coprmem.s
.code
.align 4
; Basic copr memory tests which also test the various
; addressing modes and completers.
;
; We could/should test some of the corner cases for register and
; immediate fields. We s
www.eeworm.com/read/345992/3193780
h isoaddrs.h
/* isoaddrs.h - ISO addressing */
/*
* $Header: /f/iso/h/RCS/isoaddrs.h,v 5.0 88/07/21 14:39:01 mrose Rel $
*
*
* $Log$
*/
/*
* NOTICE
*
* Acquisition, use, and distribution of this
www.eeworm.com/read/340665/3267353
s coprmem.s
.code
.align 4
; Basic copr memory tests which also test the various
; addressing modes and completers.
;
; We could/should test some of the corner cases for register and
; immediate fields. We s
www.eeworm.com/read/298558/3862983
h acenic_np.h
#ifndef _ACENIC_H_
#define _ACENIC_H_
/*
* Addressing:
*
* The Tigon uses 64-bit host addresses, regardless of their actual
* length, and it expects a big-endian format. For 32 bit systems the
*
www.eeworm.com/read/447738/1697277
s coprmem.s
.code
.align 4
; Basic copr memory tests which also test the various
; addressing modes and completers.
;
; We could/should test some of the corner cases for register and
; immediate fields. We s
www.eeworm.com/read/395929/2429555
s coprmem.s
.code
.align 4
; Basic copr memory tests which also test the various
; addressing modes and completers.
;
; We could/should test some of the corner cases for register and
; immediate fields. We s
www.eeworm.com/read/387891/8648754
c qpel.c
/*
this is optimized for sh, which have post increment addressing (*p++)
some cpu may be index (p[n]) faster than post increment (*p++)
*/
#define LD(adr) *(uint32_t*)(adr)
#
www.eeworm.com/read/283587/9004610
c qpel.c
/*
this is optimized for sh, which have post increment addressing (*p++)
some cpu may be index (p[n]) faster than post increment (*p++)
*/
#define LD(adr) *(uint32_t*)(adr)
#