代码搜索:AddIn

找到约 533 项符合「AddIn」的源代码

代码结果 533
www.eeworm.com/read/448253/7535966

jpr roomcontroller.jpr

www.eeworm.com/read/302931/13824704

vhd addm1224.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity addm1224 is port(hms,addin,clk1khz:in std_logic; m12_24,addout:out std_logic); end addm1224; architecture
www.eeworm.com/read/485155/6566203

c ad7714.c

#include #include sbit ADCLK = P1^0; sbit ADCS = P1^1; sbit ADDRDY= P1^2; sbit ADDOUT= P1^3; sbit ADDIN = P1^4; void delay(unsigned int k) { unsigned int i=0;
www.eeworm.com/read/186470/8931723

srg vsext.srg

[HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Shared Tools\Addin Designer\Microsoft Development Environment] [HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Shared Tools\Addin Designer\Microsoft Development Enviro
www.eeworm.com/read/186470/8932086

srg vbext.srg

[HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Shared Tools\Addin Designer\Visual Basic\Visual Basic 6.0] @="HKEY_CURRENT_USER\\Software\\Microsoft\\Visual Basic\\6.0" // VB Supported Add-In load behavior
www.eeworm.com/read/368127/9710905

cvsignore .cvsignore

Debug Release *.aps *.ncb *.opt *.plg *.scc *.WW *.layout *.clw *.lib *.mod *.chm *.rcb *.positions *.suo *.~* Spelly_i.c SpellyTypes.h Addin_i.c
www.eeworm.com/read/368127/9711035

cpp stdafx.cpp

/***************************************************************************/ /* NOTE: */ /* This document is copyright (c) by Oz So
www.eeworm.com/read/133111/14054330

vbp erwinspy_sample.vbp

Type=Exe Reference=*\G{00020430-0000-0000-C000-000000000046}#2.0#0#..\..\..\..\WINNT\System32\stdole2.tlb#OLE Automation Reference=*\G{490B97D1-FCB8-11D2-90A1-0010A4F2AD9E}#4.0#0#W:\ERwin\Bin\32\SCA
www.eeworm.com/read/416926/11009402

vhd wrapper_norm_seq.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity wrapper_norm_seq is generic( sh_reg_w :integer); port( clk: in std_logic;
www.eeworm.com/read/416926/11009552

vhd wrapper_norm.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity wrapper_norm is generic( sh_reg_w :integer); port( clk: in std_logic; nd