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COUNT EQU 0x40003100 AREA Example1,CODE,READONLY ENTRY CODE32 START LDR R1,=COUNT MOV R0,#0 STR R0,[R1] LOOP LDR R1,=COUNT LDR R0,[R1] ADD R0,R0,#1

PROMGEN: Xilinx Prom Generator G.23 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. promgen -w -p mcs -c FF -o E:\fpga_program\ise6.1\tst//ARM1 -u 0 E:\fpga_program\ise6.1\tst\top.bit -x

// PROMGEN: Xilinx Prom Generator G.23 // Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. DATE 05/23/07-22:29 SOURCE E:\fpga_program\ise6.1\tst//ARM1.mcs DEVICE XCF04S SIGN

// E:\ISE6.1\TST // Verilog Test fixture created by // HDL Bencher 6.1i // Mon Apr 30 19:11:30 2007 // // Notes: // 1) This test fixture has been automatically generated from // your Test Be

:020000040000FA :10000000FFFFFFFF5599AA660C000180000000E089 :100010000C800680000000220C8004800000FCA7F9 :100020000C800380808203C90C0003800000000064 :100030000C000180000000900C0004800000000013 :10