代码搜索：1Hz
找到约 197 项符合「1Hz」的源代码
代码结果 197
www.eeworm.com/read/306208/13749254
vhd count60.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count60 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/306208/13749262
vhd count24.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count24 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/151963/12156707
v clkdiv1s.v
//-------分频子模块--------//
//输入20MHz，输出1Hz
module clkdiv1s(clkin,clkout);
parameter clk_count_max=20000000-1;// 2^25=33554432
input clkin;
output clkout;
reg clkout;
reg[24:0] clk_count
www.eeworm.com/read/252463/12281267
_c timer1._c
//ICC-AVR application builder : 2007-5-6 21:30:57
// Target : M16
// Crystal: 8.0000Mhz
//TIMER1 initialize - prescale:64
// WGM: 10) PWM phz correct, TOP= ICRn
// desired value: 1Hz
// actual v
www.eeworm.com/read/252463/12281337
c timer1.c
//ICC-AVR application builder : 2007-5-6 21:30:57
// Target : M16
// Crystal: 8.0000Mhz
//TIMER1 initialize - prescale:64
// WGM: 10) PWM phz correct, TOP= ICRn
// desired value: 1Hz
// actual v
www.eeworm.com/read/13816/283925
vhd count60.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count60 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/13816/283933
vhd count24.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count24 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/17522/734317
vhd measure.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--测量部分；
entity measure is
Port (clk : in std_logic; --1Hz扫描频率；
clk10
www.eeworm.com/read/17848/762344
vhd measure.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--测量部分；
entity measure is
Port (clk : in std_logic; --1Hz扫描频率；
clk10
www.eeworm.com/read/476527/1368704
vhd measure.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--测量部分；
entity measure is
Port (clk : in std_logic; --1Hz扫描频率；
clk10