代码搜索：熔丝位
找到约 10,000 项符合「熔丝位」的源代码
代码结果 10,000
www.eeworm.com/read/32129/1031348
vhd 16位加法器.vhd
LIBRARY IEEE; //调用标准库文件
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
entity add16 is //定义实体
port( //定义端口
cin : in std_logic ;
www.eeworm.com/read/32339/1033940
vhd 8位锁存器.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LATCH_8 IS
PORT(D:IN STD_LOGIC_VECTOR(0 TO 7);
OE:IN STD_LOGIC;
G:IN STD_LOGIC;
Q:OUT ST
www.eeworm.com/read/32339/1033944
vhd 8位寄存器.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG IS
PORT(D:IN STD_LOGIC_VECTOR(0 TO 7); //定义一组8个D触发器
CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(0 TO 7));
END
www.eeworm.com/read/32339/1033964
vhd 16位加法器.vhd
LIBRARY IEEE; //调用标准库文件
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
entity add16 is //定义实体
port( //定义端口
cin : in std_logic ;
www.eeworm.com/read/34198/1039698
ewb 4位加法器.ewb
Electronics Workbench Circuit File
Version: 5
Charset: ANSI
Description:
""
EncryptionType: 1
UsingVectorGraphics: 0
/JKJPCKHJLNNIBBAMLCJLCABBOOJHAGFCPCKMCKEPLGNBEIGEPDLMAKACNLIMBFHA
LHMEB
www.eeworm.com/read/38884/1117537
vhd 8位锁存器.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LATCH_8 IS
PORT(D:IN STD_LOGIC_VECTOR(0 TO 7);
OE:IN STD_LOGIC;
G:IN STD_LOGIC;
Q:OUT ST
www.eeworm.com/read/38884/1117541
vhd 8位寄存器.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG IS
PORT(D:IN STD_LOGIC_VECTOR(0 TO 7); //定义一组8个D触发器
CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(0 TO 7));
END
www.eeworm.com/read/38884/1117561
vhd 16位加法器.vhd
LIBRARY IEEE; //调用标准库文件
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
entity add16 is //定义实体
port( //定义端口
cin : in std_logic ;
www.eeworm.com/read/39475/1131982
vhd 8位锁存器.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LATCH_8 IS
PORT(D:IN STD_LOGIC_VECTOR(0 TO 7);
OE:IN STD_LOGIC;
G:IN STD_LOGIC;
Q:OUT ST
www.eeworm.com/read/39475/1131986
vhd 8位寄存器.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG IS
PORT(D:IN STD_LOGIC_VECTOR(0 TO 7); //定义一组8个D触发器
CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(0 TO 7));
END