代码搜索：时钟提取
找到约 10,000 项符合「时钟提取」的源代码
代码结果 10,000
www.eeworm.com/read/328695/3438954
vhd div5_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div5_1 is
port(clk:in std_logic;-------时钟
div5:buffer std_logic);----输出5分频信号
end;
architecture one of div
www.eeworm.com/read/328695/3439323
vhd div5.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div5 is
generic(n:integer:=5);
port(clk:in std_logic;-------时钟
div5:out std_logic);----输出5分频信号
end;
arch
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vhd div_half.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div_half is
generic(n:integer:=2);--------n为分频系数的整数部分+1
port(clk:in std_logic;--------时钟信号
div:out std_lo
www.eeworm.com/read/328695/3439383
vhd div6.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div6 is
port(clk:in std_logic;--------时钟
div6:out std_logic);----输出6分频信号
end;
architecture one of div6 is
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vhd div7.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div7 is
port(clk:in std_logic;--------时钟
div7:out std_logic);----输出7分频信号
end;
architecture one of div7 is
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vhd div12.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div12 is
port(clk:in std_logic;--------时钟
div12:out std_logic);----输出12分频信号
end;
architecture one of div1
www.eeworm.com/read/300348/3847376
c 10.4.c
#include
typedef unsigned int uint;
typedef unsigned char uchar;
sbit Sda=P1^1; //串行数据
sbit Scl=P1^2; //串行时钟
void mDelay(uchar j) //廷时
{
uint i;
for(;j>0;j--)
for(i=0;
www.eeworm.com/read/277819/4150573
cpp 8_2.cpp
#include
class Clock //时钟类声明
{
public: //外部接口
Clock(int NewH=0, int NewM=0, int NewS=0);
void ShowTime();
void operator ++(); //前置单目运算符重载
void operator ++(int); //后置单目运算符重载
pri
www.eeworm.com/read/277819/4150703
cpp 8_2.cpp
#include
class Clock //时钟类声明
{
public: //外部接口
Clock(int NewH=0, int NewM=0, int NewS=0);
void ShowTime();
void operator ++(); //前置单目运算符重载
void operator ++(int); //后置单目运算符重载
pri
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asm asmavr.asm
.include "8515def.inc"
;***** 引脚定义
.equ Data=2 ;数据
.equ Clk=3 ;时钟
.equ Cs=4 ;片选
.equ Key=1 ;键盘
;***** 全局寄存器变量
.def bitcnt=R16 ;位计数器
.def temp=R17
.def