代码搜索：废墨清零
找到约 859 项符合「废墨清零」的源代码
代码结果 859
www.eeworm.com/read/18022/770859
vhd decoder.vhd
--分频与计数
PROCESS(clk2x,clr,den)
BEGIN
IF(clr='1')THEN --清零
count17
www.eeworm.com/read/25215/846311
asm 16-5-4.asm
ORG 0000H
JMP START
ORG 1000H
START: MOV A,#5AH ;寄存器A赋值
MOV 20H,A ;保存结果
CLR A ;累加器清零
MOV 21H,A ;保存结果
JMP START ;跳转
END
www.eeworm.com/read/32279/881058
vhd clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(clk:in std_logic;-----时钟输入 20mhz
clr:in std_logic;-----清零信号
en:in std_logic;------暂停信号
www.eeworm.com/read/32279/881937
vhd clock_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock_1 is
port(clk:in std_logic;----时钟输入 1khz
clr:in std_logic;----清零
en:in std_logic;-----暂停
www.eeworm.com/read/32279/883440
vhd xl_generate.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xl_generate is
port(clk:in std_logic;-----时钟
clr:in std_logic;-----清零
dout:out std_logic);----输出端
en
www.eeworm.com/read/32279/883990
vhd piso4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity piso4 is
port(clk:in std_logic;----时钟
clr:in std_logic;----清零
din:in std_logic_vector(3 downto 0);---
www.eeworm.com/read/32279/884710
vhd lifo_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lifo_1 is
port(clr:in std_logic;------清零信号
push:in std_logic;-----压栈
pop:in std_logic;------出栈
www.eeworm.com/read/32279/885726
vhd lifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lifo is
port(clr:in std_logic;--------清零信号
push:in std_logic;-------压栈信号
pop:in std_logic;--------出栈信
www.eeworm.com/read/28911/1012828
+
/*-----------------------------------------------
名称：秒表
内容：1、程序目的：使用定时器学习秒表计时，中断0控制走表，中断1控制清零
2、硬件要求：数码管、晶振12M
------------------------------------------------*/
#include
www.eeworm.com/read/39267/1124076
vhd clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(clk:in std_logic;-----时钟输入 20mhz
clr:in std_logic;-----清零信号
en:in std_logic;------暂停信号