代码搜索：多信号
找到约 10,000 项符合「多信号」的源代码
代码结果 10,000
www.eeworm.com/read/4710/39310
asm 报警防盗.asm
ORG 0000H
AJMP MAIN
ORG 0050H
MAIN: MOV P1,#0FFH
ACALL DD3
LOOP: JNB P3.4,LOOP;判断VT是否有信号
ACALL DL;延时防抖动
JB P3.4,START;有信号则启动
AJMP
www.eeworm.com/read/7225/109673
asm 报警防盗.asm
ORG 0000H
AJMP MAIN
ORG 0050H
MAIN: MOV P1,#0FFH
ACALL DD3
LOOP: JNB P3.4,LOOP;判断VT是否有信号
ACALL DL;延时防抖动
JB P3.4,START;有信号则启动
AJMP
www.eeworm.com/read/7268/114416
asm 报警防盗.asm
ORG 0000H
AJMP MAIN
ORG 0050H
MAIN: MOV P1,#0FFH
ACALL DD3
LOOP: JNB P3.4,LOOP;判断VT是否有信号
ACALL DL;延时防抖动
JB P3.4,START;有信号则启动
AJMP
www.eeworm.com/read/13400/275703
asm 报警防盗.asm
ORG 0000H
AJMP MAIN
ORG 0050H
MAIN: MOV P1,#0FFH
ACALL DD3
LOOP: JNB P3.4,LOOP;判断VT是否有信号
ACALL DL;延时防抖动
JB P3.4,START;有信号则启动
AJMP
www.eeworm.com/read/17631/743970
vhd clk_1hz.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_1hz is
port(
clk10k:in std_logic; ------时钟信号10khZ
clk1hz:out std_logic); -----频率信号输出1Hz
www.eeworm.com/read/32279/879518
vhd clk_1hz.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_1hz is
port(
clk10k:in std_logic; ------时钟信号10khZ
clk1hz:out std_logic); -----频率信号输出1Hz
www.eeworm.com/read/26198/955587
asm 报警防盗.asm
ORG 0000H
AJMP MAIN
ORG 0050H
MAIN: MOV P1,#0FFH
ACALL DD3
LOOP: JNB P3.4,LOOP;判断VT是否有信号
ACALL DL;延时防抖动
JB P3.4,START;有信号则启动
AJMP
www.eeworm.com/read/27335/983334
asm 报警防盗.asm
ORG 0000H
AJMP MAIN
ORG 0050H
MAIN: MOV P1,#0FFH
ACALL DD3
LOOP: JNB P3.4,LOOP;判断VT是否有信号
ACALL DL;延时防抖动
JB P3.4,START;有信号则启动
AJMP
www.eeworm.com/read/39267/1122536
vhd clk_1hz.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_1hz is
port(
clk10k:in std_logic; ------时钟信号10khZ
clk1hz:out std_logic); -----频率信号输出1Hz
www.eeworm.com/read/461648/1551931
m program_16_02.m
%生成含噪正弦信号
N=1024;
t=1:N;
sig=sin(0.03*t);
figure(1);
plot(t,sig,'LineWidth',2);xlabel('时间 t/s');ylabel('幅值 A');
%叠加信号
x=sig+randn(1,N);
figure(2)
plot(t,x,'LineWidth',2);xlabel('时间 t/s');ylab