代码搜索:信号链

找到约 10,000 项符合「信号链」的源代码

代码结果 10,000
www.eeworm.com/read/276966/10691532

c m16pwm-led.c

//////////////////////////////////////////////////////////////////////////////// //ICC-AVR application builder : 2006-8-1 上午 08:05:37 // Target : M16 // Crystal: 16.0000Mhz // ADc2采集转把信号 ////////
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bak m16pwm-led.c.bak

//////////////////////////////////////////////////////////////////////////////// //ICC-AVR application builder : 2006-8-1 上午 08:05:37 // Target : M16 // Crystal: 8.0000Mhz // ADc2采集转把信号 /////////
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m exa030307.m

%--------------------------------------------------------------------------------------- % exa030307.m, for example 3.3.7 and fig 3.3.7 % 说明多普勒信号的WVD; % % 注:在该程序中,用到了子程序 tfrwv.m, % 还要用到
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m exa030306.m

%--------------------------------------------------------------------------------------- % exa030306.m, for example 3.3.6 and fig 3.3.6 % 说明高斯线性调频信号的WVD; % % 注:在该程序中,用到了子程序 tfrpwv.m, %
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m exa030307.m

%--------------------------------------------------------------------------------------- % exa030307.m, for example 3.3.7 and fig 3.3.7 % 说明多普勒信号的WVD; % % 注:在该程序中,用到了子程序 tfrwv.m, % 还要用到
www.eeworm.com/read/466855/7022119

m exa030306.m

%--------------------------------------------------------------------------------------- % exa030306.m, for example 3.3.6 and fig 3.3.6 % 说明高斯线性调频信号的WVD; % % 注:在该程序中,用到了子程序 tfrpwv.m, %
www.eeworm.com/read/298277/7969120

cpp main.cpp

/************************************************************************ * file name: main.cpp * description: 使用类摸板,使你的信号可以方便地更改为各种数据类型。 * * modification history * ------------------
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m system_upsend_1.m

%※ 数 据 发 送 端 ※%输出OQPSK信号 %************************************************************************** clc; clear all; close all; %*** 产生随机数字比特流x***% amplitude=1; longth=16*8; sourcedata=ampli
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txt 2.txt

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity digital_clk is port(clk:in std_logic;--------------------------------------------------时钟信号 clr:in
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txt ok.txt

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity digital_clk is port(clk:in std_logic;--------------------------------------------------时钟信号 clr:in