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VHDL/FPGA/Verilog This is UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.
This is UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.
VHDL/FPGA/Verilog This is UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.
This is UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.
VHDL/FPGA/Verilog This is IDEA encryption Algorithm. Tested on Sparton 3 xilinx FPGA.
This is IDEA encryption Algorithm. Tested on Sparton 3 xilinx FPGA.
微处理器开发 XILINX edk开发的基本教程
XILINX edk开发的基本教程，给出一个例子，可以快速入门
文章/文档 tutorial of xilinx ip core
tutorial of xilinx ip core
软件工程 Xilinx foundation2.1中文教程。。。。
Xilinx foundation2.1中文教程。。。。
VHDL/FPGA/Verilog vga code for xilinx
vga code for xilinx
单片机开发 This is a counter led example developed in ISE.
This is a counter led example developed in ISE.
VHDL/FPGA/Verilog This code is a FIFO memory vhdl developed in ISE Software
This code is a FIFO memory vhdl developed in ISE Software
VHDL/FPGA/Verilog This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA.
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavor on top of an already complex protocol. The implementation is described and its pe ...