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可编程逻辑 XAPP806 -决定DDR反馈时钟的最佳DCM相移

This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microproces ...
https://www.eeworm.com/dl/kbcluoji/40078.html
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可编程逻辑 XAPP944 - 将Xilinx CoolRunner-II CPLD用作数据流开关

  This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” se ...
https://www.eeworm.com/dl/kbcluoji/40092.html
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可编程逻辑 XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器

  Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum ...
https://www.eeworm.com/dl/kbcluoji/40096.html
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可编程逻辑 XAPP708 -133MHz PCI-X到128MB DDR小型DIMM存储器桥

  The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Spec ...
https://www.eeworm.com/dl/kbcluoji/40099.html
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可编程逻辑 Verilog编码中的非阻塞性赋值

  One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assi ...
https://www.eeworm.com/dl/kbcluoji/40125.html
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可编程逻辑 FPGA设计重利用方法(Design Reuse Methodology)

  FPGAs have changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost sensitive designs. FPGAs had also been too expensive and tooslow for many a ...
https://www.eeworm.com/dl/kbcluoji/40133.html
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可编程逻辑 扩频通信芯片STEL-2000A的FPGA实现

针对传统集成电路(ASIC)功能固定、升级困难等缺点,利用FPGA实现了扩频通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核实现NCO模块,在下变频模块调用了硬核乘法器并引入CIC滤波器进行低通滤波,给出了DQPSK解调的原理和实现方法,推导出一种简便的引入?仔/4固定相移的实现方法。采用模块化的设计方法使用VHDL语言 ...
https://www.eeworm.com/dl/kbcluoji/40234.html
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可编程逻辑 基于Verilog HDL设计的多功能数字钟

本文利用Verilog HDL 语言自顶向下的设计方法设计多功能数字钟,突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点,并通过Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成综合、仿真。此程序通过下载到FPGA 芯片后,可应用于实际的数字钟显示中。 关键词:Verilog HDL;硬件描述语言;FPGA Abstract: In this ...
https://www.eeworm.com/dl/kbcluoji/40390.html
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可编程逻辑 pci e PCB设计规范

This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on b ...
https://www.eeworm.com/dl/kbcluoji/40445.html
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测试测量 产品检测中裕度和校准的乐趣

Abstract: This application note presents an overview of electronic margining and its value in detectingpotential system failures before a product ships from the factory. It is a calibration method that effectivelypredicts and allows adjustments to improve product quality. Margining also can be use ...
https://www.eeworm.com/dl/544/41612.html
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