搜索：vHD - 虫虫下载站

VHDL/FPGA/Verilog vhdl编写

vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output ...

https://www.eeworm.com/dl/663/292193.html

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嵌入式/单片机编程  在FPGA的嵌入式picoblaze设计中使用到的汇编器

在FPGA的嵌入式picoblaze设计中使用到的汇编器，在DOS下就可方便使用，方法：首先进行DOS命令窗，进行工作目录，运行kcpsm3 <filename>.psm 编译通过将生成VHD文件

https://www.eeworm.com/dl/647/313563.html

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VHDL/FPGA/Verilog 四位十进制频率计设计包含测频控制器（TESTCTL）

四位十进制频率计设计包含测频控制器（TESTCTL），4位锁存器(REG4B)，十进制计数器（CNT10）的原程序(vhd)，波形文件(wmf ),包装后的元件(bsf)。顶层原理图文件（Block1.bdf）和波形。

https://www.eeworm.com/dl/663/369459.html

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VHDL/FPGA/Verilog 交通灯控制器编码

交通灯控制器编码，源描述的编译顺序tlc.vhd，est_vector.vhd

https://www.eeworm.com/dl/663/391803.html

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VHDL/FPGA/Verilog 空调系统有限状态自动机编码

空调系统有限状态自动机编码，各个源描述的编译顺序conditioner.vhd，conditioner_stim.vhd

https://www.eeworm.com/dl/663/391804.html

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VHDL/FPGA/Verilog 是codic算法实现atan的virilog程序

是codic算法实现atan的virilog程序，模块结构如下：Core Structure: sc_corproc.vhd->p2r_cordic.vhd->p2r_cordicpipe.vhd

https://www.eeworm.com/dl/663/399122.html

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VHDL/FPGA/Verilog The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontro

The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the license agreement is stated in the main VHDL file, PICCPU.VHD and com ...

https://www.eeworm.com/dl/663/406293.html

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VHDL/FPGA/Verilog Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical and the sub-circuits can be used as smaller benchmarks.

https://www.eeworm.com/dl/663/416926.html

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VHDL/FPGA/Verilog Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested i

Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to ASCII code.

https://www.eeworm.com/dl/663/436194.html

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其他  此文件为EDA的8位分频器

此文件为EDA的8位分频器，但可以用于不同位分频器，如：1位到10位等，用Quartus软件来，以文件VHD格式编译即可

https://www.eeworm.com/dl/534/466578.html

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