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C/C++语言编程  基于（英蓓特）STM32V100的看门狗程序

This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent ...

https://www.eeworm.com/dl/503/37359.html

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可编程逻辑  采用TÜV认证的FPGA开发功能安全系统

This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This T&Uuml;V-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development e ...

https://www.eeworm.com/dl/kbcluoji/39304.html

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可编程逻辑  Create a 1-Wire Master with Xilinx PicoBlaze

Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wir ...

https://www.eeworm.com/dl/kbcluoji/39318.html

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可编程逻辑  Nios II定制指令用户指南

&nbsp;&nbsp;&nbsp;&nbsp; Nios II定制指令用户指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequen ...

https://www.eeworm.com/dl/kbcluoji/39394.html

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可编程逻辑  XAPP694-从配置PROM读取用户数据

This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in t ...

https://www.eeworm.com/dl/kbcluoji/40049.html

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可编程逻辑  XAPP228 -Virtex器件内的四端口存储器

This application note describes how the existing dual-port block memories in the Spartan&trade;-IIand Virtex&trade; families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the blockmemory in ...

https://www.eeworm.com/dl/kbcluoji/40055.html

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可编程逻辑  XAPP098 - Spartan FPGA低成本、高效率串行配置

This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration ci ...

https://www.eeworm.com/dl/kbcluoji/40059.html

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可编程逻辑  XAPP806 -决定DDR反馈时钟的最佳DCM相移

This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microproces ...

https://www.eeworm.com/dl/kbcluoji/40078.html

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可编程逻辑  XAPP944 - 将Xilinx CoolRunner-II CPLD用作数据流开关

&nbsp; This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the &ldquo;VHDLCode&rdquo; se ...

https://www.eeworm.com/dl/kbcluoji/40092.html

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可编程逻辑  XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器

&nbsp; Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan&reg;-6 FPGAs togenerate spread-spectrum ...

https://www.eeworm.com/dl/kbcluoji/40096.html

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