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VHDL/FPGA/Verilog The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode
The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated
with Micron SDRAM models. The design is verified with timing constraints at
115 MHZ.
嵌入式/单片机编程 Back in 2002, the 6502 disappeared out of all catalogues. Wanted to know, if it s possible to buil
Back in 2002, the 6502 disappeared out of all catalogues.
Wanted to know, if it s possible to build a binary compatible CPU with the things I had in the drawer:
74LS parts, 27C512 EPROMs and a fast static RAM from an old 80386 motherboard.
Now here the results.
Note, that the Bus timing is diff ...
其他 A technical trading system comprises a set of trading rules that can be used to generate trading sig
A technical trading system comprises a set of trading rules that can be used to generate trading signals. In general, a simple trading system has one or two parameters that determine the timing of trading signals. Each rule contained in a trading system is the results of parameterizations.
(Source ...
文件格式 This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was rea
This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 &micro m CMOS process and it shows a power advantage of a factor 4 compared to a recent synchronous implementation in the same technology. The chip is fully bit compatible with the sync ...
Linux/Unix编程 linux下用C语言写的聊天程序！/*BUG and NOTE: Not join protect to Shared Memory Segments,example Semaphore Array
linux下用C语言写的聊天程序！/*BUG and NOTE:
Not join protect to Shared Memory Segments,example Semaphore Arrays.
Not check the parameters validity.
When transmit may be error.
If the client program no right exit,others cannot know,the service program shouldbe check the client program whether exist t ...
其他书籍 Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book descr
Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and
techniques used towards ASIC chip synthesis, physical synthesis, formal
verification and static timing analysis, using the Synopsys suite of tools.
电子书籍 The emphasis of this book is on real-time application of Synopsys tools, used to combat various pro
The emphasis of this book is on real-time application of Synopsys tools, used
to combat various problems seen at VDSM geometries. Readers will be
exposed to an effective design methodology for handling complex, submicron
ASIC designs. Significance is placed on HDL coding styles,
synthesis and optimi ...
软件设计/软件工程 If you need a simple program to time onscreen events this is it. Just click the window and it will
If you need a simple program to time onscreen events
this is it. Just click the window and it will start timing. Click again
and it will stop.
Delphi控件源码 a real time counter component for delphi applications. You will notice that normal timer function
a real time counter component for delphi applications.
You will notice that normal timer functions in delphi is not enough for microseconds timing. This component let you get microseconds