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通讯/手机编程 wince6.0平台上的任务管理器,功能类似于windows的任务管理器. In order to develop applications for Windows Mobile 6.x from
wince6.0平台上的任务管理器,功能类似于windows的任务管理器.
In order to develop applications for Windows Mobile 6.x from within Visual Studio 2005 or 2008, you need to download a separate SDK from Microsoft. The SDK also ships with a full featured emulator, a powerful and indispensable tool to test y ...
数据结构 一个拼写检查程序
一个拼写检查程序，用来检查你的输入的文件中的单词是否拼写错误，并给你给出可能的拼写建议。（用Hashset实现）（卡耐基梅隆大学ssd5数据结构Option Exercise4答案）
程序参数设置（第一个为要输入的词库文件，本例中是wordlist.txt, 第二个为要检查的文件，必须为txt格式，本例中用test.txt来检查） ...
VxWorks Vxworks 下的视频采集程序
Vxworks 下的视频采集程序，该驱动程序是PCI类视频卡，测试程序为：test.cpp 通过初始化后，运行UTL_LVE("1.mpg",5,1)，将视频文件保存为1.mpg。 其中1.mpg为文件名，5为时间秒，1为mode。
其他 这是读好的ORL 和YALE人脸库数据
这是读好的ORL 和YALE人脸库数据， 用LODA加载后， 变量train 代表是训练样本， test 代码是测试样本。
单片机开发 LXI Standards Documents are developed within the LXI Consortium and LXI Technical Working Groups sp
LXI Standards Documents are developed within the LXI Consortium and LXI Technical Working
Groups sponsored by the LXI Consortium Board of Directors. The LXI Consortium develops its
standards through a consensus development process modeled after the American National Standards
Institute, which brings ...
百货/超市行业 一个模拟沃尔玛柜台结账的排队论仿真
一个模拟沃尔玛柜台结账的排队论仿真，相当于一个M/M/C系统，用event driven思路写成。
VHDL/FPGA/Verilog The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontro
The Synthetic PIC
Verion 1.1
This a VHDL synthesizable model of a simple PIC 16C5x microcontroller.
It is not, and is not intended as, a high fidelity circuit simulation.
This package includes the following files. Note that the license agreement
is stated in the main VHDL file, PICCPU.VHD and com ...
数学计算 observable distribution grid are investigated. A distribution grid is observable if the state of th
observable distribution grid are investigated. A distribution
grid is observable if the state of the grid can be fully determined.
For the simulations, the modified 34-bus IEEE test feeder is used.
The measurements needed for the state estimation are generated
by the ladder iterative technique. Two ...
VHDL/FPGA/Verilog Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuff
Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel
conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a
simplified UTMI interface. Currently doesn t do any error checking in
the RX section [should probably check for bit unstuffing errors].
Otherwise complete and fully ...