搜索：system-level - 虫虫下载站

可编程逻辑  Allegro FPGA System Planner中文介绍

　　完整性高的FPGA-PCB系统化协同设计工具　　Cadence OrCAD and Allegro FPGA System Planner便可满足较复杂的设计及在设计初级产生最佳的I/O引脚规划，并可透过FSP做系统化的设计规划，同时整合logic、schematic、PCB同步规划单个或多个FPGA pin的最佳化及layout placement，借由整合式的界面以减少重复在design及P ...

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可编程逻辑  Verilog_HDL的基本语法详解（夏宇闻版）

&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Verilog_HDL的基本语法详解（夏宇闻版）:Verilog HDL是一种用于数字逻辑电路设计的语言。用Verilog HDL描述的电路设计就是该电路的Verilog HDL模型。Verilog HDL既是一种行为描述的语言也是一种结构描述的语言。这也就是说，既可以用电路的功能描述也可以用元器件和它们之 ...

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可编程逻辑  《器件封装用户向导》赛灵思产品封装资料

Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes a ...

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可编程逻辑  WP200-将Spartan-3 FPGA用作远程数码相机的低成本控制器

&nbsp; The introduction of Spartan-3&trade; devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the &ldquo;almostfreestage.&rdquo; With these new FPGAs falling under $20, involume, with over 1 million system gates, and under $5for ...

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可编程逻辑  VHDL,Verilog,System verilog比较

&nbsp; 本文简单讨论并总结了VHDL、Verilog，System verilog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers ...

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