搜索结果

找到约 5,688 项符合 system verilog 的查询结果

Linux/Unix编程 file system in user space ! It s very good!

file system in user space ! It s very good!
https://www.eeworm.com/dl/619/223304.html
下载: 157
查看: 1035

Linux/Unix编程 openGFS , a kind of file system.

openGFS , a kind of file system.
https://www.eeworm.com/dl/619/223310.html
下载: 58
查看: 1104

Linux/Unix编程 ISCSI target.It can be used to make up a IPSAN system.

ISCSI target.It can be used to make up a IPSAN system.
https://www.eeworm.com/dl/619/223317.html
下载: 72
查看: 1053

Linux/Unix编程 LFS.This is a kind of file system.

LFS.This is a kind of file system.
https://www.eeworm.com/dl/619/223319.html
下载: 131
查看: 1076

通讯编程文档 In addition to individual algorithm, Demonstration System is a "data structure" (C language version)

In addition to individual algorithm, Demonstration System is a "data structure" (C language version) book algorithm corresponding to the code (CPP) and the test operating procedures (VC + +6.0 to the EXE). Through the system can demonstrate that the algorithm source code and operating results
https://www.eeworm.com/dl/646/223339.html
下载: 166
查看: 1043

其他书籍 Specification of Signalling System N0.7

Specification of Signalling System N0.7
https://www.eeworm.com/dl/542/223410.html
下载: 190
查看: 1047

行业发展研究 A system simulation environment in Matlab/Simulink of RFID is constructed in this paper. Special at

A system simulation environment in Matlab/Simulink of RFID is constructed in this paper. Special attention is emphasized on the analog/RF circuit.Negative effects are concerned in the system model,such as phase noise of the local oscillator,TX-RX coupling,reflection of the environment, AWGN noise,DC ...
https://www.eeworm.com/dl/692/223565.html
下载: 83
查看: 1081

VHDL/FPGA/Verilog 基于Verilog 的电子日历与电子时钟程序

基于Verilog 的电子日历与电子时钟程序,可以进行调日期、星期、时间的分钟与小时,通过几种模式来显示日历与时间。
https://www.eeworm.com/dl/663/223925.html
下载: 55
查看: 1060

VHDL/FPGA/Verilog 基于Verilog的数码管模拟扫描程序

基于Verilog的数码管模拟扫描程序,分为两种显示方式,一种是数码管逐个显示,另一个是所有数码管一起显示。
https://www.eeworm.com/dl/663/223927.html
下载: 168
查看: 1064

VHDL/FPGA/Verilog 一种新的FIFO实现方法,verilog描述

一种新的FIFO实现方法,verilog描述,通过modelsim 6.0 仿真,Quartue综合
https://www.eeworm.com/dl/663/223999.html
下载: 153
查看: 1026