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嵌入式/单片机编程 verilog程序
verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过
嵌入式/单片机编程 verilog实现电子时钟模块
verilog实现电子时钟模块，输入60Hz时钟信号和复位，输出时分秒，共6位，每位7段输出用于驱动
嵌入式/单片机编程 I2C总线verilog实现源码
I2C总线verilog实现源码，可以完整实现I2C bus的基本功能
单片机开发 usb1.1的对sd卡的读写的verilog代码,攻大家参考设计.
usb1.1的对sd卡的读写的verilog代码,攻大家参考设计.
J2ME J2ME中RMS（Record Manager System）的使用解析
J2ME中RMS（Record Manager System）的使用解析
通讯/手机编程 This m file models an UWB system using BPSK. The receiver is a correlation receiver with a LPF integ
This m file models an UWB system using BPSK. The receiver is a correlation receiver with a LPF integrator and comparators for threshhold selection.
系统设计方案 This was the public transportation inquiry system software engineering design documents, including t
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of designs documents, made the comprehensive analysis to the public transportation systems engineering to design , ...
系统设计方案 This was the public transportation inquiry system software engineering design documents, including t
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of designs documents, made the comprehensive analysis to the public transportation systems engineering to design , ...