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单片机编程 PCA9549 Octal bus switch with
The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determi ...
单片机编程 PCA9548A 8 channel I2C bus swi
The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An ...
单片机编程 8-bit I2C-bus and SMBus IO port with reset
The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for
SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register,
8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption
and a high-impedance open-dra ...
嵌入式综合 6小时学会labview
6小时学会labview,
labview Six Hour Course – Instructor Notes
 
This zip file contains material designed to give students a working knowledge of labview in a 6 hour timeframe. The contents are:
Instructor Notes.doc – this document.
labviewIntroduction-SixHour.ppt – a PowerPoint presentati ...
单片机开发 This firmware translates a PS/2 mouse to a USB mouse. The translator firmware is entirely interrup
This firmware translates a PS/2 mouse to a USB mouse. The translator
firmware is entirely interrupt driven (with the exception of sending the
data via USB to the host.) An interrupt is generated when the PS/2 start
bit is received, at which time the firmware will begin its receive routine.
In ad ...
其他书籍 Verilog and VHDL状态机设计
Verilog and VHDL状态机设计，英文pdf格式
State machine design techniques for Verilog and VHDL
Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in
engineer. This paper will discuss a var ...
编译器/解释器 this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 compu
this a pack include source code for quartus 2.
It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 ...
VHDL/FPGA/Verilog rc5的decryption
rc5的decryption，同样带state machine，同样有四个状态
VHDL/FPGA/Verilog The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i
The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until ...
VHDL/FPGA/Verilog it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have
it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.