搜索：spartan - 虫虫下载站

其他书籍  简单的硬件设计实验

简单的硬件设计实验，此试验可作为使用 Xilinx Platform Studio (XPS)创建简单系统的指导，此试验以 Spartan-3E为目标板。

https://www.eeworm.com/dl/542/332629.html

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其他书籍  创建基本应用程序

创建基本应用程序，本实验指导我们通过处理器创建一个基本的应用程序。应用程序将控制Spartan-3E starter kit上的LEDs。你将添加一个 OPB BRAM 控制器，和修改OPB BRAM中原有的连接部分插入文本。最后你将会发现系统就像你当初设计的一样运行。 ...

https://www.eeworm.com/dl/542/332634.html

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VHDL/FPGA/Verilog M_UART 介绍了通用异步收发器（UART）的原理

M_UART 介绍了通用异步收发器（UART）的原理，并以可编程逻辑器件FPGA为核心控制部件，基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程完成UART的设计。经测试，该设计完全达到了设计要求。

https://www.eeworm.com/dl/663/337194.html

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VHDL/FPGA/Verilog xilinx官方PCIcore 有详细说明文档

xilinx官方PCIcore 有详细说明文档，支持Spartan，Vertex

https://www.eeworm.com/dl/663/350770.html

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VHDL/FPGA/Verilog Xilinx is disclosing this Specification ? 第 1 章“EMIF 概述”

Xilinx is disclosing this Specification ? 第 1 章“EMIF 概述”，概述 Texas Instruments EMIF。 ? 第 2 章“Virtex-II 系列或 Spartan-3 FPGA 到 EMIF 的设计”描述将 TI TMSC6000 EMIF 连接到 Virtex?-II 系列或 Spartan?-3 FPGA 的实现。 ? 第 3 章“Virtex-4 FPGA 到 EMIF 的设计” 描述将 TI TMS320C64x EMIF 连接 ...

https://www.eeworm.com/dl/663/375615.html

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VHDL/FPGA/Verilog It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spa

It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.

https://www.eeworm.com/dl/663/416383.html

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VHDL/FPGA/Verilog Pong is a mixed schematic, VHDL, Verilog project featuring the PS2 and VGA monitor connections of

Pong is a mixed schematic, VHDL, Verilog project featuring the PS2 and VGA monitor connections of the Xilinx\Digilent Spartan-3 demo board.

https://www.eeworm.com/dl/663/418551.html

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其他书籍  This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware

This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx庐 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit da ...

https://www.eeworm.com/dl/542/418811.html

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VHDL/FPGA/Verilog Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested i

Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to ASCII code.

https://www.eeworm.com/dl/663/436194.html

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VHDL/FPGA/Verilog FPGA 并行NOR FLash的操作相关

FPGA 并行NOR FLash的操作相关，很实用的，基于Xilinx SPartan-3

https://www.eeworm.com/dl/663/436378.html

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