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单片机开发 Example program with AVR assembler. Purpose: Education->Assembler->Simple Watch ATMega8 and
Example program with AVR assembler.
Purpose: Education->Assembler->Simple Watch
ATMega8 and 1 relay. Relay will be on after 7day:00hour:00minute:00 second after power on.
Coded by Basri KUL (I Coded it my microprocessor classes)
多国语言处理 CRFsuite is a very fast implmentation of the Conditional Random Fields (CRF) algorithm. It handles t
CRFsuite is a very fast implmentation of the Conditional Random Fields (CRF) algorithm. It handles tens of thousands sentences in merely one second.
In comparison to CRF++, CRFSuite yields substantially better efficiency performance
matlab例程 Matlab script for solution to the driven cavity problem on a staggered grid using a divergence formu
Matlab script for solution to the driven cavity problem on a staggered grid using a divergence formulation and second-order Runge-Kutta time integration.
VC书籍 In c++ risks is a reference to a variable which exists i.e. one 2nd name for the same variable. Thi
In c++ risks is a reference to a variable which exists i.e. one 2nd name for the same variable.
This program is broken up into functions.露the function hand constitutes the entrance point of the program, firstly there is the function message which us affiche hello , and the second function produce ...
VC书籍 这是MFC Windows程序设计（第2版）
这是MFC Windows程序设计（第2版），书上的代码。第14章，计时器，CLOCK应用程序，空闲处理的编程，供大家参考。
Java编程 Generate Possion Dis. step1:Generate a random number between [0,1] step2:Let u=F(x)=1-[(1/
Generate Possion Dis.
step1:Generate a random number between [0,1]
step2:Let u=F(x)=1-[(1/e)x]
step3:Slove x=1/F(u)
step4:Repeat Step1~Step3 by using different u,you can get x1,x2,x3,...,xn
step5:If the first packet was generated at time [0], than the
second packet will be generated at time ...
单片机开发 三星程式范例
三星程式范例，八位元的
timer, counter, serial I/O, clock switching, power down, key scan, A to D, software generated LCD control, ...
VHDL/FPGA/Verilog Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design docu
Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
Linux/Unix编程 Novell.Press.Linux.Kernel.Development linux内核开发的经典书籍之一 The Linux kernel is one of the most interes
Novell.Press.Linux.Kernel.Development
linux内核开发的经典书籍之一
The Linux kernel is one of the most interesting yet least understood open-source projects. It is also a basis for developing new kernel code. That is why Sams is excited to bring you the latest Linux kernel development information fro ...
其他嵌入式/单片机内容 This is program with source code to convert ascii text files to the maxicode barcode standard.
This is program with source code to convert ascii text files to the maxicode barcode standard.
The input file consists of two columns. The first column represents a code and the second column is a string enclosed in quotes. The
codes for the first column are as follows: PM, SM, CC, MO, SC, ...