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数值算法/人工智能 FIR Filter Design This chapter treats the design of linear-phase FIR filters. The assignments are
FIR Filter Design
This chapter treats the design of linear-phase FIR filters. The assignments are
divided in two parts, the first part focuses on the design of FIR filters using the
window design method while the second part focuses on design
VHDL/FPGA/Verilog Decimal counter which is counting from 256 to 0. After that there will appear logic "1" in out. You
Decimal counter which is counting from 256 to 0. After that there will appear logic "1" in out. You can stop counting by pressing sequence.
I called it detonation clock :]
系统设计方案 The purpose of this project is to explore the issues and implementation of a multiple instruction st
The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second level cache, and maintain coherence at the L1 cache w ...
技术管理 TLC548和TLC549是以8位开关电容逐次逼近A/D转换器为基础而构造的CMOS A/D转换器。它们设 计成能通过3态数据输出和模拟输入与微处理器或外围设备串行接口。TLC548和TLC549仅
TLC548和TLC549是以8位开关电容逐次逼近A/D转换器为基础而构造的CMOS A/D转换器。它们设
计成能通过3态数据输出和模拟输入与微处理器或外围设备串行接口。TLC548和TLC549仅用输入/输出时
钟（I/O CLOCK） 和芯片选择（CS） 输入作数据控制。TLC548的最高I/O CLOCK输入频率为2.048MHz，
而TLC549的I/O CLOCK输入频率最高可达 ...
其他嵌入式/单片机内容 This is an interface program for flip flop emulation. At first pulse at the input pin the apropriate
This is an interface program for flip flop emulation. At first pulse at the input pin the apropriate output will latch and at the second pulse will release. Very short and efficient program
VHDL/FPGA/Verilog This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with
This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288).
Image resolution is not limited. It takes an RGB input (row-wise) and outp ...
DSP编程 This example sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assumi
This example sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assuming a 30Mhz XCLKIN). The
clock divider in the ADC is not used so that the ADC will see the 25Mhz on the HSPCLK. Interrupts are enabled and the EVA is setup to generate a periodic ADC SOC on SEQ1. Two ...
JavaScript This project developed in java leads us to realize a flight reservation system in order to emulate d
This project developed in java leads us to realize a flight reservation system in order to emulate databases containing the structures for the flight and for the booking. These bases extend the List interface and implements additional search鈥檚 methods.
Two interfaces provide an access to this syst ...
游戏 java3D game engine design of the source [three-dimensionalvirtualrealitynetworkprogram] - "virtual
java3D game engine design of the source
[three-dimensionalvirtualrealitynetworkprogram] - "virtual reality 3D network programming language VRML -- second-generation network programming language" CD Distribution
嵌入式/单片机编程 世界上唯一一本关于嵌入式操作系统thradX内核的书
世界上唯一一本关于嵌入式操作系统thradX内核的书，中文有翻译的第一版，这是从老外网上辛苦找来的2009年的新版第二版，大家共同学习。《Real-Time_Embedded_Multithreading_Using_ThreadX(Second Edition)》