搜索结果
找到约 618 项符合
second-CLOCK 的查询结果
微处理器开发 s3c2410 ads下的测试程序移植到 iar ewarm v5.2；包括 Please select function : 0 : Please input 1-14 to select
s3c2410 ads下的测试程序移植到 iar ewarm v5.2；包括
Please select function :
0 : Please input 1-14 to select test
1 : Real time clock display
2 : 4 key array test
3 : Buzzer test
4 : ADC test
5 : IIC EEPROM test
6 : Touchpanel test
7 : 3.5# TFT LCD 240*320 test
8 : UDA1341 play audio test
...
单片机开发 DESCRIPTION =========== This example project shows how to use the IAR Embedded Workbench for ARM
DESCRIPTION
===========
This example project shows how to use the IAR Embedded Workbench for ARM
to develop code for the Atmel AT91SAM9261 evaluation boards.
It shows basic use of parallel I/O, timer and the interrupt controller.
It starts by showing different patterns on the LED s separated by hal ...
matlab例程 采用MATLAB编写的最新三维数据图形界面
采用MATLAB编写的最新三维数据图形界面，运用GUI编程，输入函数名：volumization (data, n )即可。其中DATA的格式为：[n x m x p]；n表示显示方式： 1 - all, 2 - every second, 3 - every third。
文章/文档 The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general co
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control
and data transfer communication between ICs.
Some of the features of the I2C bus are:
&#8226 Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A
...
VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
驱动编程 This utility has two views: (a) one view that will show you the entire PnP enumeration tree of devic
This utility has two views: (a) one view that will show you the entire PnP enumeration tree of device objects, including relationships among objects and all the device s reported PnP characteristics, and (b) a second view that shows you the device objects created, sorted by driver name. There is not ...
操作系统开发 大学计算机操作系统课程设计
大学计算机操作系统课程设计，完成页面置换功能，利用clock算法
其他书籍 不错的 PERL 教程 Find a Perl programmer, and you ll find a copy of Perl Cookbook nearby. Perl Cookbook
不错的 PERL 教程
Find a Perl programmer, and you ll find a copy of Perl Cookbook nearby. Perl Cookbook is a comprehensive collection of problems, solutions, and practical examples for anyone programming in Perl. The book contains hundreds of rigorously reviewed Perl "recipes" and thousands of examp ...
其他行业 Z是模型一单位雨衰值,也是不考虑衰减因子的单位雨衰值 F是First,即第一模型的情况 F16 F165 F17分别是16GHz 16.5GHz 17GHz的情况,是模型一大气层下总雨衰值
Z是模型一单位雨衰值,也是不考虑衰减因子的单位雨衰值
F是First,即第一模型的情况
F16 F165 F17分别是16GHz 16.5GHz 17GHz的情况,是模型一大气层下总雨衰值
F18km是模型一下18km实例的雨衰值
S是Second,即第二模型的情况
S16 S165 S17分别是16GHz 16.5GHz 17GHz的情况,是模型二大气层下总雨衰值
S16m S165m S17m分别是16G ...