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ARM LPC4300系列ARM双核微控制器产品数据手册
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU ...
可编程逻辑 怎样使用Nios II处理器来构建多处理器系统
怎样使用Nios II处理器来构建多处理器系统
Chapter 1. Creating Multiprocessor Nios II Systems
Introduction to Nios II Multiprocessor Systems . . . . . . . . . . . . . . 1–1
Benefits of Hierarchical Multiprocessor Systems  . . . . . . . . . . . . . . . 1–2
Nios II Multiprocessor System ...
嵌入式/单片机编程 verilog浮点乘发器
verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline
嵌入式/单片机编程 verilog浮点乘发器
verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline
系统设计方案 Wavelets have widely been used in many signal and image processing applications. In this paper, a ne
Wavelets have widely been used in many signal and image processing applications. In this paper, a new
serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet
transform, which is realised using some FIFO memory modules implementing a pixel-level ...
其他书籍 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
...
VHDL/FPGA/Verilog HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is licensed under MIT License
手册 jenkins2.10新功能总结
jenkins2.10新功能总结
Pipeline的功能总结情况
其他 A low-power pipeline FFT processor
一中低功耗的FFT设计的结构概述，采用SDF结构，以及对ROM的简化，使得达到低功耗的目的
其他 A pipeline fast fourier transform
一中流水线结构的FFT，构建的一中新的FFT，基于流水线结构使得其运行速度更快，更适合实用。