搜索：parallel output

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热门搜索： STM32 FPGA PCB设计 电路图 51单片机 嵌入式 Arduino MATLAB Verilog Python
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https://www.eeworm.com/dl/cadence/ebook/486369.html 电子书籍

AM26C31CLow Power, I CC = 100 &#402 &#8834 A Typ Operate From a Single 5-V Supply High Spee

AM26C31CLow Power, I CC = 100 &#402 &#8834 A Typ Operate From a Single 5-V Supply High Speed, t PLH = t PHL = 7 ns Typ Low Pulse Distortion, t sk(p) = 0.5 ns Typ High Output Impedance in Power-Off Conditions Improved Replacement for AM26LS31
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https://www.eeworm.com/dl/829488.html 技术资料

PW5410B_2.0.pdf规格书下载

The PW5410B is a low noise, constant frequency (1.2MHz) switched capacitor voltage doubler. Itproduces a regulated output voltage from 1.8V to 5V input with up to 100mA of output current. Lowexternal parts count (one flying capacitor and two small bypass capacitors at VIN and VOU ...
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https://www.eeworm.com/dl/829489.html 技术资料

PW5410A_2.0.pdf规格书下载

The PW5410A is a low noise, constant frequency (1.2MHz) switched capacitor voltage doubler. Itproduces a regulated output voltage from 2.7V to 5V input with up to 250mA of output current. Lowexternal parts count (one flying capacitor and two small bypass capacitors at VIN and VOU ...
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https://www.eeworm.com/dl/527/413138.html 通讯/手机编程

In this project we analyze and design the minimum mean-square error (MMSE) multiuser receiver for un

In this project we analyze and design the minimum mean-square error (MMSE) multiuser receiver for uniformly quantized synchronous code division multiple access (CDMA) signals in additive white Gaussian noise (AWGN) channels.This project is mainly based on the representation of u ...
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https://www.eeworm.com/dl/653/331959.html 嵌入式Linux

Flash中内置了一个状态寄存器（Status Register

Flash中内置了一个状态寄存器（Status Register，SR）来指示Flash的当前工作状态和各种操作是否成功。要读取SR的当前值需要向CUI发送读状态寄存器命令（Read Status Register），命令码为0x70，SR中的内容将在DQ[7:0]上输出。The Read Status Register （0x70）command causes subsequent reads to out ...
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https://www.eeworm.com/dl/534/475526.html 其他

To write data to the FIFO, present the data to be written and assert the write enable. At the next r

To write data to the FIFO, present the data to be written and assert the write enable. At the next rising edge of the clock, the data will be written. For every rising edge of the clock that the write enable is asserted, a piece of data is written into the FIFO. If the FIFO has d ...
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https://www.eeworm.com/dl/828910.html 技术资料

ADS8329 Verilog fpga 驱动源码 2.7V 至 5.5V 16 位 1MSPS 串

ADS8329 Verilog fpga 驱动源码，2.7V 至 5.5V 16 位 1MSPS 串行模数转换器 ADC芯片ADS8329数据采集的verilog代码，已经用在工程中，可以做为你的设计参考。( input clock,  input timer_clk_r, input reset,  output reg sample_over,  output reg ad_convn,  input ad_eocn,&nbs ...
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https://www.eeworm.com/dl/663/172730.html VHDL/FPGA/Verilog

这是06年4月刚刚完成的程序

这是06年4月刚刚完成的程序，从opencore.org下载而来。用vhdl语言描写，以及matlab仿真，testbench，以及在xinlinx上的综合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel dis ...
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https://www.eeworm.com/dl/665/470886.html matlab例程

Written for engineering and computer science students and practicing engineers, this book provides t

Written for engineering and computer science students and practicing engineers, this book provides the fundamental applications and mathematical techniques of signal processing. Topics covered include programming in MATLAB, filters, networking, and parallel processing. MATLAB i ...
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https://www.eeworm.com/dl/566/34689.html 嵌入式综合

PICMG_COM_0_R2_0COMe规范--原文资料

A Computer-On-Module, or COM, is a Module with all components necessary for a bootable host computer, packaged as a super component. A COM requires a Carrier Board to bring out I/O and to power up. COMs are used to build single board computer solutions and offer OEMs fast time-to ...
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