搜索：parallel interface

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https://www.eeworm.com/dl/648/439581.html 单片机开发

driver to interface AVR chip with USB port, compile with WinAVR, very cool

driver to interface AVR chip with USB port, compile with WinAVR, very cool
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https://www.eeworm.com/dl/661/371787.html FlashMX/Flex源码

SD 2.0 Memory Controller SD Bus Interface SD Controller Logic NAND Flash Controller

SD 2.0 Memory Controller SD Bus Interface SD Controller Logic NAND Flash Controller
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https://www.eeworm.com/dl/663/411765.html VHDL/FPGA/Verilog

XILINX memory interface generator. XILINX的外部存储器接口。

XILINX memory interface generator. XILINX的外部存储器接口。
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https://www.eeworm.com/dl/619/380990.html Linux/Unix编程

sqlite C++ wrapper 1.3.1,It provides a C++ interface to access sqlite database.

sqlite C++ wrapper 1.3.1,It provides a C++ interface to access sqlite database.
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https://www.eeworm.com/dl/678/425340.html 系统设计方案

R1EX24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM).

R1EX24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MNOS memory technology and CMOS process and low voltage circuitry technology. T ...
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https://www.eeworm.com/dl/534/425940.html 其他

QAM module to use in Java with an easy interface and powerful performance

QAM module to use in Java with an easy interface and powerful performance
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https://www.eeworm.com/dl/661/395566.html FlashMX/Flex源码

Update Jedec Specification Common Flash Interface (CFI) JESD68.01 (Minor Revision to JESD68, Sept

Update Jedec Specification Common Flash Interface (CFI) JESD68.01 (Minor Revision to JESD68, September 1999)
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https://www.eeworm.com/dl/655/336957.html 微处理器开发

MSP-FET430P140 Demo - USART0, SPI Interface to HC165/164 Shift Registers Description: Demonstrate

MSP-FET430P140 Demo - USART0, SPI Interface to HC165/164 Shift Registers Description: Demonstrate USART0 in two-way SPI mode. Data are read from an HC165, and same data written back to the HC164. ACLK = n/a MCLK = SMCLK = default DCO = UCLK0 = DCO/2 * USART0 control bits are in ...
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https://www.eeworm.com/dl/663/469162.html VHDL/FPGA/Verilog

This is UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.

This is UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.
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https://www.eeworm.com/dl/663/469163.html VHDL/FPGA/Verilog

This is UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.

This is UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.
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