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其他书籍 A pdf regarding, reading of bar codes from mobile phones. All types of bar codes can be read from th
A pdf regarding, reading of bar codes from mobile phones. All types of bar codes can be read from the mobile phones. It includes the details regarding, how to convert the bar codes into appropriate formats and then to verify it for the geniality.
电子技术 pll 相關paper
pll 相關paper,可參考!
內含各模塊架構及模擬,歡迎參考!
技术资料 CPCI_E标准规范 CompactPCI® Express Specification
CPCI_E标准规范 CompactPCI® Express SpecificationThe documents in this section may be useful for reference when reading the specification. The  revision listed for each document is the latest revision at the time this specification was published.  Newer revisions of these documents may exi ...
资料/手册 FAT32中文版.rar
hardware white paper-fat32中文资料,有参考价值
学术论文 基于ARM的多对象远程抄表系统集中器的设计与实现
智能电表、水表、煤/燃气表、热量表等大量地出现在人们的生活中,同时这些仪表的抄录工作变得越来越烦琐,工作量大,工作效率低,不仅给用户带来不便,而且会存在漏抄、误抄、估抄的现象。随着电子技术、通信技术和计算机技术的飞速发展,人工抄表已经逐步被自动抄表所代替。 集中器是一个数据集中处理器,是多对象自动抄表 ...
通讯/手机编程 DMX512-1990
灯光舞台系统的通信协议白皮书,DMX512在1990年发布时的原版白皮书-stage lighting system communication protocol White Paper
教程资料 以CPLD 芯片进行十字路口的交通灯的设计
摘要:本文主要介绍以CPLD 芯片进行十字路口的交通灯的设计,用CPLD 作为交通灯控制器的主控芯片,采用VHDL\r\n语言编写控制程序,利用CPLD的可重复编程和在动态系统重构的特性,大大地提高了数字系统设计的灵活性和通用性。\r\n关键词:CPLD;VHDL;交通灯控制器\r\n中图分类号:TP39\r\nAbstract :This paper introduces ...
allegro Verilog Coding Style for Efficient Digital Design
 
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All the ...
allegro State Machine Coding Styles for Synthesis
 
本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点,Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concernin ...
allegro Verilog编码中的非阻塞性赋值
 
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assi ...