搜索结果

找到约 1,144 项符合 multi-Digital 的查询结果

汇编语言 Test program to loop on Successive Approximation A-to-D conversion. Allows digital codes and resul

Test program to loop on Successive Approximation A-to-D conversion. Allows digital codes and resulting DAC output to be viewed on scope.
https://www.eeworm.com/dl/644/181086.html
下载: 96
查看: 1057

其他 Various routines that simulate or compute aspects of digital communication systems

Various routines that simulate or compute aspects of digital communication systems
https://www.eeworm.com/dl/534/181380.html
下载: 125
查看: 1048

VHDL/FPGA/Verilog Digital Clock in Assembly 我的一个大学满分VHDL作品

Digital Clock in Assembly 我的一个大学满分VHDL作品,数字石英钟的模拟程序。
https://www.eeworm.com/dl/663/181863.html
下载: 63
查看: 1063

其他 book:simulation and softeware radiao for mibole code:psk-based digital transmission schemes ofdm

book:simulation and softeware radiao for mibole code:psk-based digital transmission schemes ofdm transmission technology cdma transmission technology multiple access protocals cellular telecommunication systems
https://www.eeworm.com/dl/534/182909.html
下载: 184
查看: 1121

电子书籍 Digital cellular telecommunications system (Phase 2+) AT command set for GSM Mobile Equipment (ME)

Digital cellular telecommunications system (Phase 2+) AT command set for GSM Mobile Equipment (ME) (GSM 07.07 version 7.4.0 Release 1998)
https://www.eeworm.com/dl/cadence/ebook/183422.html
下载: 63
查看: 1047

VHDL/FPGA/Verilog advanced digital design with the verilog hdl

advanced digital design with the verilog hdl
https://www.eeworm.com/dl/663/184601.html
下载: 187
查看: 1082

单片机开发 MODE_Switch1Processing multi-interrupt request needs to set the priority of these interrupt requests

MODE_Switch1Processing multi-interrupt request needs to set the priority of these interrupt requests. The IRQ flags of the 7 interrupt are controlled by the interrupt event occurring. But the IRQ flag set doesn t mean the system to execute the interrupt vector. The IRQ flags can be triggered by the ...
https://www.eeworm.com/dl/648/184633.html
下载: 72
查看: 1079

通讯编程文档 Study of Digital Modulation Schemes using DDS

Study of Digital Modulation Schemes using DDS
https://www.eeworm.com/dl/646/185210.html
下载: 198
查看: 1054

邮电通讯系统 关于Digital Signal Process中FIR

关于Digital Signal Process中FIR , IIR滤波器的设计与实现
https://www.eeworm.com/dl/690/186153.html
下载: 151
查看: 1054

VHDL/FPGA/Verilog My thesis entitled "fpga digital clock," immature, to enlighten

My thesis entitled "fpga digital clock," immature, to enlighten
https://www.eeworm.com/dl/663/188411.html
下载: 44
查看: 1069