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系统设计方案 The development of a data acquisition card based on USB bus is introduced in this article.It first d
The development of a data acquisition card based on USB bus is introduced in this article.It first describes the configuration and principle of this card in the part of hardware design,and then the application program and device driver in the part of software design.Data acquisition program in firmw ...
Java编程 java生成xml,model,jsp,主要用于springside+struts+ibatis
java生成xml,model,jsp,主要用于springside+struts+ibatis
文章/文档 D3D光照模型.大家好好学习,多多交流. Lights model
D3D光照模型.大家好好学习,多多交流.
Lights model
软件设计/软件工程 IPCAM Design document based on TI DaVinci
IPCAM Design document based on TI DaVinci
其他 The Microsoft® Active Directory™ Service Interfaces (ADSI) Software Development Kit (SDK) is
The Microsoft&reg Active Directory&#8482 Service Interfaces (ADSI) Software Development Kit (SDK) is a client-side product, based on the Component Object Model (COM), that defines a directory service model and a set of COM interfaces that enables Microsoft Windows NT&reg /Windows&reg 2000 and Window ...
软件设计/软件工程 In a preemptive priority based RTOS, priority inversion problem is among the major sources of deadl
In a preemptive priority based RTOS, priority inversion
problem is among the major sources of deadline
violations. Priority inheritance protocol is one of the
approaches to reduce priority inversion. Unfortunately,
RTOS like uC/OS can’t support priority inheritance
protocol since it does not allow ...
文章/文档 图像处理的关于Snakes : Active Contour Models算法和水平集以及GVF的几篇文章
图像处理的关于Snakes : Active Contour Models算法和水平集以及GVF的几篇文章，文章列表为：
[1]Snakes Active Contour Models.pdf
[2]Multiscale Active Contours.pdf
[3]Snakes, shapes, and gradient vector flow.pdf
[4]Motion of level sets by mean curvature I.pdf
[5]Spectral Stability of Local Deformations Sp ...
软件工程 基于DDS的信号发生器的设计与开发 The Design and Development of Function Generator Based on DDS
基于DDS的信号发生器的设计与开发
The Design and Development of Function Generator Based on DDS
VHDL/FPGA/Verilog 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard mem
一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench
VHDL/FPGA/Verilog Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of d
Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of
designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.