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在综合分析谐波励磁无刷同步发电机励磁控制系统的基础上,对其励磁控制策略进行了研究,开发了一套基于DSP( TMS320F2812) 控制的新型柴油发电机励磁控制系统,该系统采用参数自适应模糊PID 控制励磁,选用交流采样方式实时检测各信号的瞬时特性,系统仿真结果以及在1 台25 kW 工频柴油发电机上的试验结果证明了该控制器具有较好 ...

设计一种应用于某全地形ATV车载武器装置中的中控系统，该系统设计是以TMS320F2812型DSP为核心，采用模块化设计思想，对其硬件部分进行系统设计，能够完成对武器装置高低、回转方向的运动控制，实现静止或行进状态中对目标物的测距，自动瞄准以及按既定发射模式发射弹丸和各项安全性能检测等功能。通过编制相应的软件，对其 ...

　　中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html 　　Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture 　 　The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class ...

Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes a ...

This application note describes how to implement the Bus LVDS (BLVDS) interface in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS example.

Design techniques for electronic systems areconstantly changing. In industries at the heart of thedigital revolution, this change is especially acute.Functional integration, dramatic increases incomplexity, new standards and protocols, costconstraints, and increased time-to-market pressureshave bo ...

Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. ...

WP369可扩展式处理平台-各种嵌入式系统的理想解决方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-c ...

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX  and area optimizat ...

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接  The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and ...