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找到约 79 项符合 guidelines 的查询结果

其他书籍 Introduction to I/O Kit Device Driver Design Guidelines Chapter 1 The libkern C++ Runtime Chapter

Introduction to I/O Kit Device Driver Design Guidelines Chapter 1 The libkern C++ Runtime Chapter 2 libkern Collection and Container Classes Chapter 3 The IOService API Chapter 4 Making Hardware Accessible to Applications Chapter 5 Kernel-User Notification Chapter 6 Displaying Localized Information ...
https://www.eeworm.com/dl/542/461126.html
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嵌入式/单片机编程 Guidelines on Commercial Use of RFID Technology

Guidelines on Commercial Use of RFID Technology
https://www.eeworm.com/dl/647/471285.html
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嵌入式/单片机编程 This is our version of tetris, with "guidelines" as an option. These will allow you to easily se whe

This is our version of tetris, with "guidelines" as an option. These will allow you to easily se where the pieces will fall, be highlighing the columns that the falling piece is at the given moment. Enjoy!
https://www.eeworm.com/dl/647/475036.html
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书籍 Guidelines+for+Electrical+Transmission+Line

Since the original publication of Manual 74 in 1991, and the preceding “Guidelines for Transmission Line Structural Loading” in 1984, the understanding of structural loadings on transmission line structures has broadened signifi cantly. However, improvements in computational capa- bility have enab ...
https://www.eeworm.com/dl/522321.html
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资料/手册 VGA时序标准08版

有最新高清标准1920*1080,Proposed VESA and Industry Standards and Guidelines for Computer Display Monitor Timing (DMT) Version 1.0, Revision 12p, Draft 3
https://www.eeworm.com/dl/541/14087.html
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allegro Verilog Coding Style for Efficient Digital Design

  In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All the ...
https://www.eeworm.com/dl/allegro/20110.html
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allegro Verilog编码中的非阻塞性赋值

  One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assi ...
https://www.eeworm.com/dl/allegro/20129.html
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模拟电子 高精度I2C实时时钟的设计

Abstract: This application note presents an overview of the operational characteristics of accurate I²C real-time clocks (RTCs),including the DS3231, DS3231M, and DS3232. It focuses on general application guidelines that facilitate use of device resources forpower management, I²C communi ...
https://www.eeworm.com/dl/571/21071.html
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模拟电子 用于信号调理的微电路

  Low power operation of electronic apparatus has becomeincreasingly desirable. Medical, remote data acquisition,power monitoring and other applications are good candidatesfor battery driven, low power operation. Micropoweranalog circuits for transducer-based signal conditioningpresent a sp ...
https://www.eeworm.com/dl/571/21356.html
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PCB相关 PCB Design Considerations and Guidelines for 0.4mm and 0.5mm WLPs

Abstract: Using a wafer-level package (WLP) can reduce the overall size and cost of your solution.However when using a WLP IC, the printed circuit board (PCB) layout can become more complex and, ifnot carefully planned, result in an unreliable design. This article presents some PCB designconsidera ...
https://www.eeworm.com/dl/501/21612.html
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