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文件格式 datasheet ADC14155 full
datasheet ADC14155 full
文章/文档 datasheet adc12c170man full
datasheet adc12c170man full
其他书籍 This User’s Manual is intended for experienced users and integrators with hardware knowledge of per
This User’s Manual is intended for experienced users and integrators with
hardware knowledge of personal computers. If you are not sure about any
description in this User’s Manual, please consult your vendor before further
handling.
手机短信编程 This is full set of procedures used to communicate with any GSM module for SMS sending/receiving (
This is full set of procedures used to communicate with
any GSM module for SMS sending/receiving (it uses standard AT commands).
Original code is for ATMega162 microcontroller, but code is general to
be easy ported to others platforms.
Code can be compiled with IAR AVR compiler.
通讯编程文档 "Hard to find" full description of ContactID protocol from Ademco used by many home security devices
"Hard to find" full description of ContactID protocol from Ademco used by many home security devices to send messages to CMS (Central Monitoring Station) about security events.
Has full technical description and can be used to easy make CMS communication module that sends info from your alarm syst ...
电子书籍 full description of TMS320C6711 DSK kit
full description of TMS320C6711 DSK kit
USB编程 USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.
USBHostSlave is a USB 1.1 host and Device IP core.
– Supports full speed (12Mbps) and low speed (1.5Mbps) operation.
– USB Device has four endpoints, each with their own independent FIFO.
– Supports the four types of USB data transfer control, bulk, interrupt, and isochronous
transfers.
– Host ...
软件设计/软件工程 avr atmel orcad full version library
avr atmel orcad full version library
VHDL/FPGA/Verilog Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design docu
Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
VHDL/FPGA/Verilog This application note explains the process of eveloping and debugging a hardware abstraction layer
This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios&#174 II system. The various software development stages are illustrated using the Altera_Avalon_UART as ...