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行业发展研究 full of joy to see my dat here
full of joy to see my dat here
软件工程 Designing Embedded Hardware Ebook By John Catsoulis If you want to build your own embedded system
Designing Embedded Hardware Ebook By John Catsoulis
If you want to build your own embedded system, or tweak an existing one, this invaluable book gives you the understanding and practical skills you need.
matlab例程 full wave rectifierDuring the period from 伪 to 蟺, the input voltage vs input current is are positive
full wave rectifierDuring the period from 伪 to 蟺, the input voltage vs input current is are positive and the power flows from supply to the load. The converter is said to be operated at rectification mode .During the period from 蟺 to 蟺+伪 , the input voltage vs is negative and the input current ...
Delphi控件源码 EMS Advanced.export. components full source
EMS Advanced.export. components full source
VHDL/FPGA/Verilog I2C core code in Hardware descrption language so as enable a cpld/fpga to be programmed for specific
I2C core code in Hardware descrption language so as enable a cpld/fpga to be programmed for specific customized applications of our requirment & make the pcb work to meet the application requirements.
软件工程 description of evoting protocols to be implemented via very secure codes and its bugs and full revie
description of evoting protocols to be implemented via very secure codes and its bugs and full reviews.
Java编程 Here is the DHTML tree example with full source code
Here is the DHTML tree example with full source code
其他 ecomimerce on line shop with full functions,this is a useful php source code.
ecomimerce on line shop with full functions,this is a useful php source code.
游戏 An interactive water fountain. A realistic water source in your pocket with full control. Contro
An interactive water fountain.
A realistic water source in your pocket with full control.
Controls:
UP/DOWN - go closer/further
LEFT/RIGHT - rotate
# - stop rotation
1/7 - rotate camera up/down
3/9 - change water pressure
4/6 - change water rendering complexity
2/8 - ascend/descend
0 - bullet time ...
VHDL/FPGA/Verilog This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with
This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288).
Image resolution is not limited. It takes an RGB input (row-wise) and outp ...