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教程资料 基于Xilinx FPGA的双输出DC/DC转换器解决方案

  Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The ...
https://www.eeworm.com/dl/fpga/doc/32612.html
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可编程逻辑 基于Xilinx FPGA的双输出DC/DC转换器解决方案

  Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The ...
https://www.eeworm.com/dl/kbcluoji/40111.html
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技术资料 Spartan-6 datasheet Spartan系列FPGA芯片

Spartane-6 LXand LXT FPGAs are available in various speed grades, with -3 having the highest performance. The DC and AC electrical parameters of the Automotive XA Spartan-6 FPGAs and Defense-grade Spartan-6Q FPGAs devices are equivalent to the commercial specifications except where noted. The timing ...
https://www.eeworm.com/dl/835901.html
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教程资料 an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysi

1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis\r\n2. fpga implemention of a median filter\r\n3. fpga implementation of digital filters\r\n4.hardware acceleration of edge detection algorithm on fpgas
https://www.eeworm.com/dl/fpga/doc/17585.html
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教程资料 关于FPGA流水线设计的论文

关于FPGA流水线设计的论文\r\nThis work investigates the use of very deep pipelines for\r\nimplementing circuits in FPGAs, where each pipeline\r\nstage is limited to a single FPGA logic element (LE). The\r\narchitecture and VHDL design of a parameterized integer\r\na
https://www.eeworm.com/dl/fpga/doc/18638.html
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教程资料 WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案

WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案: High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
https://www.eeworm.com/dl/fpga/doc/32625.html
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可编程逻辑 WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案

WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案: High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
https://www.eeworm.com/dl/kbcluoji/40106.html
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教程资料 XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器

  Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum ...
https://www.eeworm.com/dl/fpga/doc/32595.html
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可编程逻辑 XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器

  Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum ...
https://www.eeworm.com/dl/kbcluoji/40096.html
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电子书籍 The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and i

The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator so ...
https://www.eeworm.com/dl/cadence/ebook/176911.html
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