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找到约 405 项符合 floating-Point 的查询结果

其他嵌入式/单片机内容 This lab exercise will introduce you to AccelDSP’s floating- to fixed-point conversion features. Acc

This lab exercise will introduce you to AccelDSP’s floating- to fixed-point conversion features. AccelDSP will automatically generate a fixed-point representation of a floating-point design. This process is controllable by using quantize directives.
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单片机编程 MPLAB C30用户指南(英文)

MPLAB C30用户指南(英文) HIGHLIGHTSThe information covered in this chapter is as follows:• About this Guide• Recommended Reading• Troubleshooting• The Microchip Web Site• Development Systems Customer Notification Service• Customer Support Document LayoutThe documen ...
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教程资料 WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案

WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案: High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
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ARM LPC4300系列ARM双核微控制器产品数据手册

The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU ...
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可编程逻辑 WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案

WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案: High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
https://www.eeworm.com/dl/kbcluoji/40106.html
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语音压缩 The Audio File Library provides a uniform programming interface to standard digital audio file form

The Audio File Library provides a uniform programming interface to standard digital audio file formats. This library allows the processing of audio data to and from audio files of many common formats (currently AIFF, AIFF-C, WAVE, NeXT/Sun .snd/.au, IRCAM, AVR, Amiga IFF/8SVX, and NIST SPHERE). The ...
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其他书籍 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in

关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 ...
https://www.eeworm.com/dl/542/179429.html
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数学计算 Two functions, num2bin and bin2num are provided. num2bin takes a double and converts it to a binary

Two functions, num2bin and bin2num are provided. num2bin takes a double and converts it to a binary string representation. bin2num is its inverse operation. It can be used in a numerical analysis course when floating point arithmetic is discussed.
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其他嵌入式/单片机内容 This getting started exercise will guide you through the step-by-step process of transforming a MATL

This getting started exercise will guide you through the step-by-step process of transforming a MATLAB floating-point model into a hardware module that can be implemented in silicon (FPGA or ASIC). The design is a general purpose FIR filter taken from the AccelDSP Examples directory.
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DSP编程 CCS编程环境 使用的是汇编加C的混合编程方法: The programme of the Correlation Algorithm. Using INT2 to get the input s

CCS编程环境 使用的是汇编加C的混合编程方法: The programme of the Correlation Algorithm. Using INT2 to get the input signal. Array x, in first step, is the input signal produced by programme, in next step, is the input signal get from A/D, the length is 128, 32-bit floating point. Array y, in first s ...
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