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单片机编程  PCA9541 2 to 1 I2C-bus master

The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on separate I2C ...

https://www.eeworm.com/dl/502/31003.html

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单片机编程  PCA9555 16bit I2C-bus and SMBu

The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed toenhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvementsinclude higher drive capability, 5 V I/O tolerance, lo ...

https://www.eeworm.com/dl/502/31013.html

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单片机编程  8-bit I2C-bus and SMBus IO port with reset

The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption and a high-impedance open-dra ...

https://www.eeworm.com/dl/502/31025.html

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单片机编程  Using the Stellaris Microcontr

Luminary Micro Stellaris&#8482; microcontrollers that are equipped with an analog-to-digital converter(ADC), use an innovative sequence-based sampling architecture designed to be extremely flexible,yet easy to use. This application note describes the sampling architecture of the ADC. Sinceprogrammer ...

https://www.eeworm.com/dl/502/31064.html

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单片机编程  Clocking Options for Stellaris

The main oscillator allows either a crystal or single-ended input clock signal. Cost-sensitiveapplications typically use an external crystal with the on-chip oscillator circuit since it is the mostcost-effective solution. It is also possible to use the internal oscillator to clock the device after t ...

https://www.eeworm.com/dl/502/31067.html

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单片机编程  UART测试程序-AT91SAM9260

UART测试程序-AT91SAM9260://* The software is delivered "AS IS" without warranty or condition of any//* kind, either express, implied or statutory. This includes without//* limitation any warranty or condition with respect to merchantability or//* fitness for any particular purpose, or against the in ...

https://www.eeworm.com/dl/502/31164.html

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单片机编程  Input Signal Rise and Fall Tim

All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, howeve ...

https://www.eeworm.com/dl/502/31376.html

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单片机编程  I2C slave routines for the 87L

The 87LPC76X Microcontroller combines in a small package thebenefits of a high-performance microcontroller with on-boardhardware supporting the Inter-Integrated Circuit (I2C) bus interface.The 87LPC76X can be programmed both as an I2C bus master, aslave, or both. An overview of the I2C bus and descr ...

https://www.eeworm.com/dl/502/31386.html

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教程资料  XAPP806 -决定DDR反馈时钟的最佳DCM相移

This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microproces ...

https://www.eeworm.com/dl/fpga/doc/32600.html

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教程资料  XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接&nbsp; The I/Os in Xilinx&reg; 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and ...

https://www.eeworm.com/dl/fpga/doc/32622.html

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