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J2ME 利用SyncML开发客户端程序的中间件

利用SyncML开发客户端程序的中间件,J2ME版本。 This library is a collection of basic utilities for: object serialization and persistence on the RMS, Logging and string manipulation. This document describes the Funambol JavaME Common API library, which purpose is giving support and providing basic fun ...
https://www.eeworm.com/dl/660/267433.html
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GPS编程 There are numerous MATLAB m-files included in this software package. Thus, the the authors have bund

There are numerous MATLAB m-files included in this software package. Thus, the the authors have bundled all files and sample data in a *.zip file (KTHorb.zip). The Readme.txt file describes the directories created when the .zip file is unpacked. The file Matlab_implementation.doc (or Matlab_implemen ...
https://www.eeworm.com/dl/693/268541.html
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其他书籍 The IA-32 Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture (Order Numbe

The IA-32 Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture (Order Number 245470) is part of a three-volume set that describes the architecture and programming environment of all IA-32 Intel Architecture processors.
https://www.eeworm.com/dl/542/281026.html
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其他书籍 The IA-32 Intel Architecture Software Developer’s Manual, Volume 2: Instruction Set Reference (Orde

The IA-32 Intel Architecture Software Developer’s Manual, Volume 2: Instruction Set Reference (Order Number 245471) is part of a three-volume set that describes the architecture and programming environment of all IA-32 Intel&reg Architecture processors. the IA-32 Intel Architecture Software Develop ...
https://www.eeworm.com/dl/542/281028.html
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其他书籍 The IA-32 Software Developer’s Manual, Volume 3: System Programming Guide (Order Number 245472), is

The IA-32 Software Developer’s Manual, Volume 3: System Programming Guide (Order Number 245472), is part of a three-volume set that describes the architecture and programming environment of all IA-32 Intel&reg Architecture processors. The IA-32 Software Developer’s Manual, Volume 3, describes the ...
https://www.eeworm.com/dl/542/281030.html
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其他 A .zip file contains a series of scripts that were used in the MathWorks webinar "Using MATLAB to De

A .zip file contains a series of scripts that were used in the MathWorks webinar "Using MATLAB to Develop Portfolio Optimization Models." The scripts generate 3D efficient frontiers for a universe of 44 stocks with time as the third axis. Additional scripts perform various ex-ante and ex-post analys ...
https://www.eeworm.com/dl/534/289027.html
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VC书籍 This book is a complete reference to the C programming language and the C runtime library. As a Nuts

This book is a complete reference to the C programming language and the C runtime library. As a Nutshell book, its purpose is to serve as a convenient, reliable companion for C programmers in their day-to-day work. It describes all the elements of the language and illustrates their use with numerous ...
https://www.eeworm.com/dl/686/310658.html
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Java书籍 Writing Robust Java Code The AmbySoft Inc. Coding Standards for Java v17.01d Scott W. Ambler Sof

Writing Robust Java Code The AmbySoft Inc. Coding Standards for Java v17.01d Scott W. Ambler Software Process Mentor This Version: January 15, 2000 Copyright 1998-1999 AmbySoft Inc.Purpose of this White Paper This white paper describes a collection of standards, conventio code. They are based on so ...
https://www.eeworm.com/dl/656/349056.html
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VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift ...
https://www.eeworm.com/dl/663/361747.html
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VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift ...
https://www.eeworm.com/dl/663/361749.html
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