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数值算法/人工智能 使用奇异值分解算法的prony算法-single value decomposition based prony algorithm
使用奇异值分解算法的prony算法-single value decomposition based prony algorithm
单片机开发 FM1702的例子程序 Chip type : ATmega16L Program type : Application Clock frequency : 7.372800 MHz Memo
FM1702的例子程序
Chip type : ATmega16L
Program type : Application
Clock frequency : 7.372800 MHz
Memory model : Small
External SRAM size : 0
Data Stack size : 256
嵌入式/单片机编程 Design of Image Collection System Based on High-speed PCI Bus基于PCI总线的高速图像采集系统设计
Design of Image Collection System Based
on High-speed PCI Bus基于PCI总线的高速图像采集系统设计
通讯编程文档 Design of High Speed Multichannel Data Gathering System Based on FPGA基于FPGA的高速多通道数据采集系统的设计
Design of High Speed Multichannel Data Gathering System Based on FPGA基于FPGA的高速多通道数据采集系统的设计
STL Export a vertices/faces patch to an STL triangular mesh.This is based heavily on Bill McDonald s pre
Export a vertices/faces patch to an STL triangular mesh.This is based heavily on Bill McDonald s previous work, simply enabling his output functions for a different form of input.
其他 A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation
A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
VHDL/FPGA/Verilog Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.
Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.
嵌入式/单片机编程 RTL8091 10 based ethernet interface programming application note
RTL8091 10 based ethernet interface programming application note
VxWorks CIRRUS LAN(tm) CS8900 VxWORKS MUX-Based ENHANCED NETWORK DRIVER (END)
CIRRUS LAN(tm) CS8900 VxWORKS MUX-Based ENHANCED NETWORK DRIVER (END)
加密解密 CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 b
CRC码产生器与校验器程序
Features ：
Executes in one clock cycle per data word
Any polynomial from 4 to 32 bits
Any data width from 1 to 256 bits
Any initialization value
Synchronous or asynchronous reset