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书籍源码 计算全息close all clc clear A=zeros(64) A(15:20,20:40)=1 A(15:50,20:25)=1 A(45:50,20:40)=1 A(30:34,
计算全息close all clc clear
A=zeros(64)
A(15:20,20:40)=1 A(15:50,20:25)=1
A(45:50,20:40)=1 A(30:34,20:35)=1
％ ppp=exp(rand(64)*pi*2*i) A=A.*ppp
％ Author s email: zjliu2001@163.com
figure imshow(abs(A),[])
Fa=fft2(fftshift(A)) Fs=fftshift(Fa)
Am=abs(Fs) ％ amplitude
Ph=angle(Fs) ％ phase
s=11 ...
Linux/Unix编程 Clear Mine扫雷游戏: 这是一个模拟扫雷游戏的vc编码程序 编码思想: 通过几个数组设定好雷区的位置
Clear Mine扫雷游戏:
这是一个模拟扫雷游戏的vc编码程序 编码思想: 通过几个数组设定好雷区的位置，自己造出几个视图类的成员函数，分析是是否有雷，以及雷的个数。
基于DirectDraw的小游戏 Koules:
Koules是基于DirectDraw的小游戏用DirectDraw,DirectSound,DirectInput的综合例子 移植自linux下游戏，原代码结构较好较 ...
电子书籍 This will give a clear description of MPLS.
This will give a clear description of MPLS.
软件工程 describe the operation of theARMcore from a product developer鈥檚 perspective with a clear emphasis o
describe the operation of theARMcore from a product developer鈥檚
perspective with a clear emphasis on software. Because we have written this book specifically
for engineers who are experienced with embedded systems development but who may be
unfamiliar with the ARM architecture, we have assumed no ...
其他书籍 It provides complete, clear, and detailed explanations of advanced electri- cal engineering concep
It provides complete,
clear, and detailed explanations of advanced electri-
cal engineering concepts illustrated with numerous
practical examples.
电子书籍 It provides complete, clear, and detailed explanations of advanced electri- cal engineering concep
It provides complete,
clear, and detailed explanations of advanced electri-
cal engineering concepts illustrated with numerous
practical examples.
编辑器/阅读器 clear Diff BC source zip file
clear Diff BC source zip file
技术管理 in this file,it will tell you how to write well and clear c file.in this file,it will tell you how t
in this file,it will tell you how to write well and clear c file.in this file,it will tell you how to write well and clear c file.
其他文档 74164 TTL八位串行入、并行输出移位寄存器
These 8-bit shift registers feature gated serial inputs andan asynchronous clear. A LOW logic le
资料/手册 74LS73.pdf
英文描述： Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
中文描述： 双下降沿触发主从JK触发器明确和互补输出