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找到约 675 项符合
board-specific 的查询结果
微处理器开发 M22A Series EV Board、M22A 系列评估板 用户手册
M22A Series EV Board、M22A 系列评估板
用户手册，带原理图及使用说明，对开发LPC2200系列产品具有一定的参考价值
VHDL/FPGA/Verilog 4-7segment led display Verilog code. Implemented at Stratix EP1S25 DSP development board.
4-7segment led display Verilog code. Implemented at Stratix EP1S25 DSP development board.
微处理器开发 IDE接口实验 Embest Teach Kit II boot success Embest 44B0X Evaluation Board(EduKit II) IDE Test Exampl
IDE接口实验
Embest Teach Kit II boot success
Embest 44B0X Evaluation Board(EduKit II)
IDE Test Example
Model Number : SUNDOM 32M
Serial Number: SN20030928-V1.02C
Version : Ver 2.0
Vendor ID :
单片机开发 Example_DUALADC_28pin CY3210-PSoCEVAL1 and CY3210-MiniEval1 Board Project
Example_DUALADC_28pin
CY3210-PSoCEVAL1 and CY3210-MiniEval1 Board Project
其他嵌入式/单片机内容 example of communication between the Cerebellum 16f877 pic board and the CMUcam
example of communication between the Cerebellum 16f877 pic board and the CMUcam
嵌入式Linux Embest Arm EduKit II Evaluation Board External Interrupt Test Example Please Select the trigger:
Embest Arm EduKit II Evaluation Board
External Interrupt Test Example
Please Select the trigger:
1 - Falling trigger
2 - Rising trigger
3 - Both Edge trigger
4 - Low level trigger
5 - High level trigger
any key to exit...
Press the buttons
push buttons may have glitch noise problem
EINT6 ...
嵌入式Linux Embest S3C44B0X Evaluation Board RTC Test Example RTC Check(Y/N)? y Set Default Time at 2004
Embest S3C44B0X Evaluation Board
RTC Test Example
RTC Check(Y/N)? y
Set Default Time at 2004-12-31 FRI 23:59:59
Set Alarm Time at 2005-01-01 00:00:01
... RTC Alarm Interrupt O.K. ...
Current Time is 2005-01-01 SAT
00:00:01
RTC Working now. To set date(Y/N)? y
Current date is (2005,01,01, ...
文章/文档 classic chess board pattern recognition!
classic chess board pattern recognition!
嵌入式/单片机编程 his design is the initial design when the board is powered-up. It increments a counter and displays
his design is the initial design when the board is powered-up. It increments a counter and displays the value on the
7-segment displays and LEDs. An image is also displayed on the VGA port.
VHDL/FPGA/Verilog Sobel--Image Filter (I). An Image filtering is made over data loaded into the on board RAM and prese
Sobel--Image Filter (I). An Image filtering is made over data loaded into the on board RAM and presented on a VGA monitor.zip