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找到约 127 项符合 beyond Compare 的查询结果

VHDL/FPGA/Verilog The FPGA can realize a more optimized Digital controller in DC/DC Converters when compare to DSPs. I

The FPGA can realize a more optimized Digital controller in DC/DC Converters when compare to DSPs. In this paper, based on the FPGA platform, The theoretical analysis, characteristics, simulation and design consideration are given. The methods to implement the digital DC/DC Converters have been rese ...
https://www.eeworm.com/dl/663/469392.html
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Java编程 these notes give an overview of beyond C to java and a good idea on how to develop applications in j

these notes give an overview of beyond C to java and a good idea on how to develop applications in java
https://www.eeworm.com/dl/633/470759.html
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其他 UCSC Kestrel and Beyond写的一篇关于SIMD的讲义,很好,很使用,也可以作为一个PPT模板使用的经典例子哦

UCSC Kestrel and Beyond写的一篇关于SIMD的讲义,很好,很使用,也可以作为一个PPT模板使用的经典例子哦
https://www.eeworm.com/dl/534/473513.html
下载: 35
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其他 compuete the fast fourier transformation of the image. it is very fast compare than fourier transfor

compuete the fast fourier transformation of the image. it is very fast compare than fourier transformation.
https://www.eeworm.com/dl/534/475124.html
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数据结构 9、优先级队列 QueueNode.h Compare.h PriorityQueue.h Test.cpp 10、串 88 MyString.h MyString.cpp

9、优先级队列 QueueNode.h Compare.h PriorityQueue.h Test.cpp 10、串 88 MyString.h MyString.cpp test.cpp 11、二叉树 BinTreeNode.h BinaryTree.h Test.cpp 12、线索二叉树 ThreadNode.h ThreadTree.h ThreadInorderIterator.h test.cpp
https://www.eeworm.com/dl/654/477928.html
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软件 beyond conpare 绿色版

beyond conpare 绿色版,代码对比工具
https://www.eeworm.com/dl/521225.html
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学术论文 基于FPGA的空时分组码的设计与实现

随着第三代移动通信系统(3G)向商业化的迈进,以及超三代(Beyond 3G) 或被称之为第四代(4G)移动通信系统的发展,对更高速率、更大容量和更好服务质量的通信系统的需求正在不断增长。另一方面,可利用的无线频谱资源是有限...
https://www.eeworm.com/dl/514/13348.html
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allegro Verilog Coding Style for Efficient Digital Design

  In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All the ...
https://www.eeworm.com/dl/allegro/20110.html
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模拟电子 音频数模转换器DAC抖动的灵敏度分析

Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequenc ...
https://www.eeworm.com/dl/571/20671.html
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模拟电子 将您的微控制器ADC升级至真正的12位性能

  Many 8-bit and 16-bit microcontrollers feature 10-bitinternal ADCs. A few include 12-bit ADCs, but these oftenhave poor or nonexistent AC specifi cations, and certainlylack the performance to meet the needs of an increasingnumber of applications. The LTC®2366 and its slowerspeed versi ...
https://www.eeworm.com/dl/571/21331.html
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